From patchwork Fri May 10 05:54:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1097836 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 450ffm1N02z9sB8 for ; Fri, 10 May 2019 15:59:12 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E2C03C21CB6; Fri, 10 May 2019 05:56:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7D245C21DAF; Fri, 10 May 2019 05:55:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 88852C21DD3; Fri, 10 May 2019 05:55:21 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lists.denx.de (Postfix) with ESMTPS id CE626C21C50 for ; Fri, 10 May 2019 05:55:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 May 2019 22:55:16 -0700 X-ExtLoop1: 1 Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by FMSMGA003.fm.intel.com with SMTP; 09 May 2019 22:55:13 -0700 Received: by ubuntu (sSMTP sendmail emulation); Fri, 10 May 2019 13:55:12 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de Date: Fri, 10 May 2019 13:54:40 +0800 Message-Id: <1557467688-73706-7-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557467688-73706-1-git-send-email-ley.foon.tan@intel.com> References: <1557467688-73706-1-git-send-email-ley.foon.tan@intel.com> Cc: Marek Vasut , Tien Fong Chee , Chin Liang See , Chee Hong Ang Subject: [U-Boot] [PATCH 06/14] arm: socfpga: agilex: Add system manager support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add system manager support for Agilex. Signed-off-by: Ley Foon Tan --- .../include/mach/system_manager.h | 6 + .../include/mach/system_manager_agilex.h | 127 ++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_agilex.h diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 171b79e238..ee693fc7a6 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -6,8 +6,14 @@ #ifndef _SYSTEM_MANAGER_H_ #define _SYSTEM_MANAGER_H_ +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ + defined(CONFIG_TARGET_SOCFPGA_AGILEX) + #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include +#endif void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h new file mode 100644 index 0000000000..3b814d67f5 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation + */ + +#ifndef _SYSTEM_MANAGER_AGILEX_ +#define _SYSTEM_MANAGER_AGILEX_ + +struct socfpga_system_manager { + /* System Manager Module */ + u32 siliconid1; /* 0x00 */ + u32 siliconid2; + u32 wddbg; + u32 _pad_0xc; + u32 mpu_status; /* 0x10 */ + u32 mpu_ace; + u32 _pad_0x18_0x1c[2]; + u32 dma; /* 0x20 */ + u32 dma_periph; + /* SDMMC Controller Group */ + u32 sdmmcgrp_ctrl; + u32 sdmmcgrp_l3master; + /* NAND Flash Controller Register Group */ + u32 nandgrp_bootstrap; /* 0x30 */ + u32 nandgrp_l3master; + /* USB Controller Group */ + u32 usb0_l3master; + u32 usb1_l3master; + /* EMAC Group */ + u32 emac_gbl; /* 0x40 */ + u32 emac0; + u32 emac1; + u32 emac2; + u32 emac0_ace; /* 0x50 */ + u32 emac1_ace; + u32 emac2_ace; + u32 nand_axuser; + u32 _pad_0x60_0x64[2]; /* 0x60 */ + /* FPGA interface Group */ + u32 fpgaintf_en_1; + u32 fpgaintf_en_2; + u32 fpgaintf_en_3; /* 0x70 */ + u32 dma_l3master; + u32 etr_l3master; + u32 _pad_0x7c; + u32 sec_ctrl_slt; /* 0x80 */ + u32 osc_trim; + u32 _pad_0x88_0x8c[2]; + /* ECC Group */ + u32 ecc_intmask_value; /* 0x90 */ + u32 ecc_intmask_set; + u32 ecc_intmask_clr; + u32 ecc_intstatus_serr; + u32 ecc_intstatus_derr; /* 0xa0 */ + u32 _pad_0xa4_0xac[3]; + u32 noc_addr_remap; /* 0xb0 */ + u32 hmc_clk; + u32 io_pa_ctrl; + u32 _pad_0xbc; + /* NOC Group */ + u32 noc_timeout; /* 0xc0 */ + u32 noc_idlereq_set; + u32 noc_idlereq_clr; + u32 noc_idlereq_value; + u32 noc_idleack; /* 0xd0 */ + u32 noc_idlestatus; + u32 fpga2soc_ctrl; + u32 fpga_config; + u32 iocsrclk_gate; /* 0xe0 */ + u32 gpo; + u32 gpi; + u32 _pad_0xec; + u32 mpu; /* 0xf0 */ + u32 sdm_hps_spare; + u32 hps_sdm_spare; + u32 _pad_0xfc_0x1fc[65]; + /* Boot scratch register group */ + u32 boot_scratch_cold0; /* store qspi ref clock */ + u32 boot_scratch_cold1; /* store osc1 clock freq */ + u32 boot_scratch_cold2; /* store fpga clock freq */ + u32 boot_scratch_cold3; + u32 boot_scratch_cold4; /* store PSCI_CPU_ON value */ + u32 boot_scratch_cold5; /* store PSCI_CPU_ON value */ + u32 boot_scratch_cold6; /* store VBAR_EL3 value */ + u32 boot_scratch_cold7; /* store VBAR_EL3 value */ + u32 boot_scratch_cold8; /* store ECC DBE register */ + u32 boot_scratch_cold9; /* store ECC DBE address */ + u32 mpfe_config; + u32 mpfe_status; + u32 _pad_0x230_0xffc[884]; + /* Pin select and pin control group */ + u32 pinsel0[40]; /* 0x1000 */ + u32 _pad_0x10a0_0x10fc[24]; + u32 pinsel40[8]; + u32 _pad_0x1120_0x112c[4]; + u32 ioctrl0[28]; + u32 _pad_0x11a0_0x11fc[24]; + u32 ioctrl28[20]; + u32 _pad_0x1250_0x12fc[44]; + /* Use FPGA mux */ + u32 rgmii0usefpga; /* 0x1300 */ + u32 rgmii1usefpga; + u32 rgmii2usefpga; + u32 i2c0usefpga; + u32 i2c1usefpga; + u32 i2c_emac0_usefpga; + u32 i2c_emac1_usefpga; + u32 i2c_emac2_usefpga; + u32 nandusefpga; + u32 _pad_0x1324; + u32 spim0usefpga; + u32 spim1usefpga; + u32 spis0usefpga; + u32 spis1usefpga; + u32 uart0usefpga; + u32 uart1usefpga; + u32 mdio0usefpga; + u32 mdio1usefpga; + u32 mdio2usefpga; + u32 _pad_0x134c; + u32 jtagusefpga; + u32 sdmmcusefpga; + u32 _pad_0x1358_0x13fc[42]; + u32 iodelay0[48]; +}; + +#endif /* _SYSTEM_MANAGER_AGILEX_ */