From patchwork Tue Feb 19 03:47:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1044416 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 443Rch52jCz9s5c for ; Tue, 19 Feb 2019 14:51:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5D1E1C21E13; Tue, 19 Feb 2019 03:51:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B2122C21FC7; Tue, 19 Feb 2019 03:47:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 48184C21F7E; Tue, 19 Feb 2019 03:47:43 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id F135AC21FC1 for ; Tue, 19 Feb 2019 03:47:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Feb 2019 19:47:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,385,1544515200"; d="scan'208";a="276049233" Received: from pg-iccf0313.altera.com ([10.104.1.136]) by orsmga004.jf.intel.com with ESMTP; 18 Feb 2019 19:47:35 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Tue, 19 Feb 2019 11:47:19 +0800 Message-Id: <1550548041-32682-6-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1550548041-32682-1-git-send-email-tien.fong.chee@intel.com> References: <1550548041-32682-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH v9 5/7] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- changes for v9 - Used ALLOC_CACHE_ALIGN_BUFFER - De-duplicated the same chunks of codes changes for v7 - Removed casting for get_fpga_filename - Removed hard coding DDR address for loading core bistream, using loadable property from FIT. - Added checking for config_pins, return if error. --- arch/arm/mach-socfpga/spl_a10.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index c97eacb..4b658c8 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2019 Altera Corporation */ #include @@ -23,6 +23,11 @@ #include #include #include +#include +#include +#include + +#define FPGA_BUFSIZ 16 * 1024 DECLARE_GLOBAL_DATA_PTR; @@ -68,11 +73,35 @@ u32 spl_boot_mode(const u32 boot_device) void spl_board_init(void) { + ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ); + /* enable console uart printing */ preloader_console_init(); WATCHDOG_RESET(); arch_early_init_r(); + + /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ + if (is_fpgamgr_user_mode()) { + int ret = config_pins(gd->fdt_blob, "shared"); + + if (ret) + return; + + ret = config_pins(gd->fdt_blob, "fpga"); + if (ret) + return; + } else if (!is_fpgamgr_early_user_mode()) { + /* Program IOSSM(early IO release) or full FPGA */ + fpgamgr_program(buf, FPGA_BUFSIZ, 0); + } + + /* If the IOSSM/full FPGA is already loaded, start DDR */ + if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) + ddr_calibration_sequence(); + + if (!is_fpgamgr_user_mode()) + fpgamgr_program(buf, FPGA_BUFSIZ, 0); } void board_init_f(ulong dummy)