From patchwork Tue Dec 18 08:54:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 1015161 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43JsKj3vszz9s3q for ; Tue, 18 Dec 2018 19:55:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 383D0C22182; Tue, 18 Dec 2018 08:54:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C8DC9C21F97; Tue, 18 Dec 2018 08:54:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A2695C21F06; Tue, 18 Dec 2018 08:54:24 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lists.denx.de (Postfix) with ESMTPS id E1658C21F06 for ; Tue, 18 Dec 2018 08:54:23 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Dec 2018 00:54:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,367,1539673200"; d="scan'208";a="101531781" Received: from angcheeh-mobl.gar.corp.intel.com (HELO localhost.localdomain) ([10.226.242.192]) by orsmga006.jf.intel.com with ESMTP; 18 Dec 2018 00:54:15 -0800 From: chee.hong.ang@intel.com To: u-boot@lists.denx.de Date: Tue, 18 Dec 2018 00:54:04 -0800 Message-Id: <1545123245-77250-4-git-send-email-chee.hong.ang@intel.com> In-Reply-To: <1545123245-77250-1-git-send-email-chee.hong.ang@intel.com> References: <1545123245-77250-1-git-send-email-chee.hong.ang@intel.com> Cc: Marek Vasut , Chee Hong Ang , Ching Liang See Subject: [U-Boot] [PATCH v6 3/4] arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: "Ang, Chee Hong" Enable 'fpga' command in u-boot. User will be able to use the FPGA command to program the FPGA on Stratix10 SoC. Signed-off-by: Ang, Chee Hong --- arch/arm/mach-socfpga/include/mach/misc.h | 4 ++-- arch/arm/mach-socfpga/misc.c | 26 ++------------------------ arch/arm/mach-socfpga/misc_arria10.c | 22 +++++++++++++++++++++- arch/arm/mach-socfpga/misc_gen5.c | 22 +++++++++++++++++++++- arch/arm/mach-socfpga/misc_s10.c | 22 ++++++++++++++++++++++ drivers/fpga/altera.c | 6 ++++++ include/altera.h | 4 ++++ 7 files changed, 78 insertions(+), 28 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 4fc9570..3964831 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -16,9 +16,9 @@ struct bsel { extern struct bsel bsel_str[]; #ifdef CONFIG_FPGA -void socfpga_fpga_add(void); +void socfpga_fpga_add(void *fpga_desc); #else -static inline void socfpga_fpga_add(void) {} +inline void socfpga_fpga_add(void *fpga_desc) {} #endif #ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index a4f6d5c..78fbe28 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -88,33 +88,11 @@ int overwrite_console(void) #endif #ifdef CONFIG_FPGA -/* - * FPGA programming support for SoC FPGA Cyclone V - */ -static Altera_desc altera_fpga[] = { - { - /* Family */ - Altera_SoCFPGA, - /* Interface type */ - fast_passive_parallel, - /* No limitation as additional data will be ignored */ - -1, - /* No device function table */ - NULL, - /* Base interface address specified in driver */ - NULL, - /* No cookie implementation */ - 0 - }, -}; - /* add device descriptor to FPGA device table */ -void socfpga_fpga_add(void) +void socfpga_fpga_add(void *fpga_desc) { - int i; fpga_init(); - for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) - fpga_add(fpga_altera, &altera_fpga[i]); + fpga_add(fpga_altera, fpga_desc); } #endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index f347ae8..430e2b4 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -37,6 +37,26 @@ static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; /* + * FPGA programming support for SoC FPGA Arria 10 + */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Altera_SoCFPGA, + /* Interface type */ + fast_passive_parallel, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + +/* + * This function initializes security policies to be consistent across + * all logic units in the Arria 10. + * @@ -73,7 +93,7 @@ void socfpga_sdram_remap_zero(void) int arch_early_init_r(void) { /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); + socfpga_fpga_add(&altera_fpga[0]); return 0; } diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6..21f5ac3 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -35,6 +35,26 @@ static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; /* + * FPGA programming support for SoC FPGA Cyclone V + */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Altera_SoCFPGA, + /* Interface type */ + fast_passive_parallel, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + +/* * DesignWare Ethernet initialization */ #ifdef CONFIG_ETH_DESIGNWARE @@ -214,7 +234,7 @@ int arch_early_init_r(void) socfpga_sdram_remap_zero(); /* Add device descriptor to FPGA device table */ - socfpga_fpga_add(); + socfpga_fpga_add(&altera_fpga[0]); #ifdef CONFIG_DESIGNWARE_SPI /* Get Designware SPI controller out of reset */ diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index e599362..113eace 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -25,6 +25,26 @@ static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /* + * FPGA programming support for SoC FPGA Stratix 10 + */ +static Altera_desc altera_fpga[] = { + { + /* Family */ + Intel_FPGA_Stratix10, + /* Interface type */ + secure_device_manager_mailbox, + /* No limitation as additional data will be ignored */ + -1, + /* No device function table */ + NULL, + /* Base interface address specified in driver */ + NULL, + /* No cookie implementation */ + 0 + }, +}; + +/* * DesignWare Ethernet initialization */ #ifdef CONFIG_ETH_DESIGNWARE @@ -125,6 +145,8 @@ int arch_misc_init(void) int arch_early_init_r(void) { + socfpga_fpga_add(&altera_fpga[0]); + return 0; } diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 9605554..7c8f518 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -39,6 +39,9 @@ static const struct altera_fpga { #if defined(CONFIG_FPGA_STRATIX_V) { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, #endif +#if defined(CONFIG_FPGA_STRATIX10) + { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL }, +#endif #if defined(CONFIG_FPGA_SOCFPGA) { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, #endif @@ -154,6 +157,9 @@ int altera_info(Altera_desc *desc) case fast_passive_parallel_security: printf("Fast Passive Parallel with Security (FPPS)\n"); break; + case secure_device_manager_mailbox: + puts("Secure Device Manager (SDM) Mailbox\n"); + break; /* Add new interface types here */ default: printf("Unsupported interface type, %d\n", desc->iface); diff --git a/include/altera.h b/include/altera.h index 233b467..22d55cf 100644 --- a/include/altera.h +++ b/include/altera.h @@ -39,6 +39,8 @@ enum altera_iface { fast_passive_parallel, /* fast passive parallel with security (FPPS) */ fast_passive_parallel_security, + /* secure device manager (SDM) mailbox */ + secure_device_manager_mailbox, /* insert all new types before this */ max_altera_iface_type, }; @@ -54,6 +56,8 @@ enum altera_family { Altera_StratixII, /* StratixV Family */ Altera_StratixV, + /* Stratix10 Family */ + Intel_FPGA_Stratix10, /* SoCFPGA Family */ Altera_SoCFPGA,