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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id z9sm37330096pfd.99.2018.12.11.23.06.41 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 23:06:42 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 23:11:19 -0800 Message-Id: <1544598686-14130-19-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544598686-14130-1-git-send-email-bmeng.cn@gmail.com> References: <1544598686-14130-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v4 18/25] riscv: Do some basic architecture level cpu initialization X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In arch_cpu_init_dm() do some basic architecture level cpu initialization, like FPU enable, etc. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v4: None Changes in v3: - only initialize mcounteren CSR for S-mode - only touch satp in M-mode U-Boot - move the implementation to arch_cpu_init_dm() Changes in v2: - use csr_set() to set MSTATUS_FS - only enabling the cycle, time, and instret counters - change to use satp arch/riscv/cpu/cpu.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index a2ebaf3..fa7d869 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include /* @@ -57,7 +58,31 @@ static int riscv_cpu_probe(void) int arch_cpu_init_dm(void) { - return riscv_cpu_probe(); + int ret; + + ret = riscv_cpu_probe(); + if (ret) + return ret; + + /* Enable FPU */ + if (supports_extension('d') || supports_extension('f')) { + csr_set(MODE_PREFIX(status), MSTATUS_FS); + csr_write(fcsr, 0); + } + + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + /* + * Enable perf counters for cycle, time, + * and instret counters only + */ + csr_write(mcounteren, GENMASK(2, 0)); + + /* Disable paging */ + if (supports_extension('s')) + csr_write(satp, 0); + } + + return 0; } int arch_early_init_r(void)