From patchwork Tue Dec 11 09:35:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010942 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vAGeHB7d"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZpz37srz9s3l for ; Tue, 11 Dec 2018 20:47:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 17270C226AF; Tue, 11 Dec 2018 09:36:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9B7F5C227FC; Tue, 11 Dec 2018 09:31:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8CB90C227E8; Tue, 11 Dec 2018 09:30:38 +0000 (UTC) Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) by lists.denx.de (Postfix) with ESMTPS id F369EC225E2 for ; Tue, 11 Dec 2018 09:30:32 +0000 (UTC) Received: by mail-pf1-f182.google.com with SMTP id q1so6851455pfi.5 for ; Tue, 11 Dec 2018 01:30:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=fNhVy94x4w2BxfS18oYZk3CN5+cTePwafuMU+DfiFAY=; b=vAGeHB7dDPjpu2MSiBNZL4ElK6S5Lfd+O0EcQ9PRIjNwEWG6Z1pj3cUbkyyjFtHWpM BOhHT4++hwkcbD3zzBKdn0qcnapSGhSxDSvPH5EIcpKvFvkLjPZlyOG+u0dbUrLolQ2a J/abG/tCrLC56rVEFbdoDRYgLb+3nlr2SZrSrPhVqJhaH8uJ9SKD06XjadJbi+uu2GRT SmIvcDO2BRDX0LRx7doymueWqxgwE7UVMKme08fKMVjyHz9j8gvYsulayGFYJ5koyHiO QzKXRuAed6MbGBVmpgnzlsaEUugAC6EMx1yj3Sv6vLqvcis81BCUvYRbSq8X+bnOH0Gh dmzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=fNhVy94x4w2BxfS18oYZk3CN5+cTePwafuMU+DfiFAY=; b=SRC0QMRfGWM1lUdfPQnv8JbY52HUtcaboP/CW3P5i2EPGhnUKnfIpWJ1k+tWA4N7dX UDZdMNDyOQdwlmc70TWjZUUMSL2TVJjTfAfV9qn65EkEeaNsXG5E22Z8vP5Yv2ShFa1/ BPTQ38QIv2IsP1WPBLqEY9xHD8Akc6uulCylR5hjZY+jOJglgo2eIYeKKhLnuYIZrevD 1hnh8wb/ay/YmHtRxlUd7VRACWqVzXTlyeYn7g0l+N3MVU7Q5GplPCMgoJvEFkN+/vF/ s7BuMFfZMc4pKMug1FGE7Y0ApEynSzi6zXjKzFY+Z3ajH/o4QeeejP2GKtOPeBurnjxG Oz+A== X-Gm-Message-State: AA+aEWZGb4Uvm8YZLmVWeoKFHIEZFUhwCpRlbLriD5nD1892JeELqYvK LrDcaMO9ZXUXmAnjuVMqQQo= X-Google-Smtp-Source: AFSGD/Wrprzms1I5LXPbqIcnO8VGm1cZ7Y1xvah/ANpumI4kiZxQjZBYNhLfOFxVrLaDjhRbvTGZ/w== X-Received: by 2002:a63:8c0d:: with SMTP id m13mr14049631pgd.422.1544520631581; Tue, 11 Dec 2018 01:30:31 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.30 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:31 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:35:01 -0800 Message-Id: <1544520901-31558-26-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 25/25] riscv: Remove ae350.dts X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is not used by any board. Remove it. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - new patch to remove ae350.dts Changes in v2: None arch/riscv/dts/ae350.dts | 229 ----------------------------------------------- 1 file changed, 229 deletions(-) delete mode 100644 arch/riscv/dts/ae350.dts diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts deleted file mode 100644 index e48c298..0000000 --- a/arch/riscv/dts/ae350.dts +++ /dev/null @@ -1,229 +0,0 @@ -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,ax25"; - model = "andestech,ax25"; - - aliases { - uart0 = &serial0; - spi0 = &spi; - }; - - chosen { - bootargs = "console=ttyS0,38400n8 debug loglevel=7"; - stdout-path = "uart0:38400n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <60000000>; - CPU0: cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv39"; - clock-frequency = <60000000>; - d-cache-size = <0x8000>; - d-cache-line-size = <32>; - CPU0_intc: interrupt-controller { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,riscv-ae350-soc"; - ranges; - - plic0: interrupt-controller@e4000000 { - compatible = "riscv,plic0"; - #address-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x0 0xe4000000 0x0 0x2000000>; - riscv,ndev=<71>; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; - }; - - plic1: interrupt-controller@e6400000 { - compatible = "riscv,plic1"; - #address-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x0 0xe6400000 0x0 0x400000>; - riscv,ndev=<1>; - interrupts-extended = <&CPU0_intc 3>; - }; - - plmt0@e6000000 { - compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7>; - reg = <0x0 0xe6000000 0x0 0x100000>; - }; - }; - - spiclk: virt_100mhz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0x0 0xf0400000 0x0 0x1000>; - clock-frequency = <60000000>; - interrupts = <3 4>; - interrupt-parent = <&plic0>; - }; - - serial0: serial@f0300000 { - compatible = "andestech,uart16550", "ns16550a"; - reg = <0x0 0xf0300000 0x0 0x1000>; - interrupts = <9 4>; - clock-frequency = <19660800>; - reg-shift = <2>; - reg-offset = <32>; - no-loopback-test = <1>; - interrupt-parent = <&plic0>; - }; - - mac0: mac@e0100000 { - compatible = "andestech,atmac100"; - reg = <0x0 0xe0100000 0x0 0x1000>; - interrupts = <19 4>; - interrupt-parent = <&plic0>; - }; - - mmc0: mmc@f0e00000 { - compatible = "andestech,atfsdc010"; - max-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; - fifo-depth = <0x10>; - reg = <0x0 0xf0e00000 0x0 0x1000>; - interrupts = <18 4>; - cap-sd-highspeed; - interrupt-parent = <&plic0>; - }; - - dma0: dma@f0c00000 { - compatible = "andestech,atcdmac300"; - reg = <0x0 0xf0c00000 0x0 0x1000>; - interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; - dma-channels = <8>; - interrupt-parent = <&plic0>; - }; - - lcd0: lcd@e0200000 { - compatible = "andestech,atflcdc100"; - reg = <0x0 0xe0200000 0x0 0x1000>; - interrupts = <20 4>; - interrupt-parent = <&plic0>; - }; - - smc0: smc@e0400000 { - compatible = "andestech,atfsmc020"; - reg = <0x0 0xe0400000 0x0 0x1000>; - }; - - snd0: snd@f0d00000 { - compatible = "andestech,atfac97"; - reg = <0x0 0xf0d00000 0x0 0x1000>; - interrupts = <17 4>; - interrupt-parent = <&plic0>; - }; - - virtio_mmio@fe007000 { - interrupts = <0x17 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe007000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe006000 { - interrupts = <0x16 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe006000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe005000 { - interrupts = <0x15 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe005000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe004000 { - interrupts = <0x14 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe004000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe003000 { - interrupts = <0x13 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe003000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe002000 { - interrupts = <0x12 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe002000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe001000 { - interrupts = <0x11 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe001000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe000000 { - interrupts = <0x10 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe000000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x88000000 0x0 0x1000>; - bank-width = <2>; - device-width = <1>; - }; - - spi: spi@f0b00000 { - compatible = "andestech,atcspi200"; - reg = <0x0 0xf0b00000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - clocks = <&spiclk>; - interrupts = <4 4>; - interrupt-parent = <&plic0>; - flash@0 { - compatible = "spi-flash"; - spi-max-frequency = <50000000>; - reg = <0>; - spi-cpol; - spi-cpha; - }; - }; -};