From patchwork Mon Dec 10 10:52:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 1010366 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43D0PB2Kwzz9s55 for ; Mon, 10 Dec 2018 21:56:14 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 065C1C22079; Mon, 10 Dec 2018 10:54:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BCE68C224BC; Mon, 10 Dec 2018 10:53:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8D268C22480; Mon, 10 Dec 2018 10:53:29 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 3813CC22492 for ; Mon, 10 Dec 2018 10:53:26 +0000 (UTC) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id wBAApovI025520; Mon, 10 Dec 2018 11:53:22 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2p85qjsyqy-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 10 Dec 2018 11:53:22 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4C01B34; Mon, 10 Dec 2018 10:53:22 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2ED1127D6; Mon, 10 Dec 2018 10:53:22 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.92) by Safex1hubcas24.st.com (10.75.90.94) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 10 Dec 2018 11:53:21 +0100 Received: from localhost (10.201.23.85) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 10 Dec 2018 11:53:25 +0100 From: Patrick Delaunay To: Date: Mon, 10 Dec 2018 11:52:42 +0100 Message-ID: <1544439166-5749-4-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544439166-5749-1-git-send-email-patrick.delaunay@st.com> References: <1544439166-5749-1-git-send-email-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-12-10_03:, , signatures=0 Cc: U-Boot STM32 Subject: [U-Boot] [PATCH 3/7] da850evm: sf: Read default speed and mode values from DT X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In case of DT boot, don't read default speed and mode for SPI from CONFIG_*, instead read from DT node. Signed-off-by: Patrick Delaunay Reviewed-by: Petr Vorel --- board/davinci/da8xxevm/da850evm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index b0b29b3..4ef454e 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -44,8 +44,15 @@ DECLARE_GLOBAL_DATA_PTR; #define CFG_MAC_ADDR_SPI_BUS 0 #define CFG_MAC_ADDR_SPI_CS 0 + +#ifdef CONFIG_DM_SPI_FLASH +/* In DM mode, speed and mode value will be taken from DT */ +#define CFG_MAC_ADDR_SPI_MAX_HZ 0 +#define CFG_MAC_ADDR_SPI_MODE 0 +#else #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3 +#endif #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)