From patchwork Tue Sep 4 01:06:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris X-Patchwork-Id: 965649 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="d+WsdqU4"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4247xC4JFSz9s3Z for ; Tue, 4 Sep 2018 11:07:59 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2FA77C21F24; Tue, 4 Sep 2018 01:07:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8A2ACC21EC8; Tue, 4 Sep 2018 01:06:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 03F3DC21C4A; Tue, 4 Sep 2018 01:06:24 +0000 (UTC) Received: from mail-it0-f65.google.com (mail-it0-f65.google.com [209.85.214.65]) by lists.denx.de (Postfix) with ESMTPS id 7B0D0C21E44 for ; Tue, 4 Sep 2018 01:06:24 +0000 (UTC) Received: by mail-it0-f65.google.com with SMTP id f14-v6so2892789ita.4 for ; Mon, 03 Sep 2018 18:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G42bwBDWu9YpicUqLLzXZLPrQEM2tpmjwFGdKC5mEUw=; b=d+WsdqU4r1Ja2ass/T8w0j/8Cn9jHnv7d/s9rX6awMZOFOMX5hMhmkzFj85vHLzDec oK4CehZQtwvtYkm+wPQ8dIoDmqF28TeifEIn1ALdo/vLaXHZH6PgaRi3uiebmHmNy3BP Rt1HnHQTqI/Ik1defM6Za6cwgkZIXdGrTXs2v1e25QCBBSR9QhgTXdZTFsKbT5TLSzj5 TzfKwWU5nBcVPrmcHEi4BhIBmyFmrQOuJccTFG4XZyl1miOpc0dbgzx+mHmKXYPVnKyQ K9xDF+Xob+nHBt4eopjPgGWElpgtbsSAF7TjF+pQEeIWGKTRYTtf6Q6iRjUTN1Oit/cf 5tgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G42bwBDWu9YpicUqLLzXZLPrQEM2tpmjwFGdKC5mEUw=; b=kd2Dvp7o/+/YBC9OuDzZS1Guh5UB8hz8u8qfqrwFeroVcbmsntMOFLEeAgK0ZgxiYz Zy9KXmDQmSzbUr/6SSbH7HmRLTxKpZBAqFat4vtp6pX8PCGaEIFkGlFtwLL4DT9v45lC fwC7WjSjPaE/hxPYnmoDgu2bY9iboQSwYThU1biUS0pH6eG5BpLl12MYYaM4dX4nodAY JiP+FqwU0eiOG+SFjusBaRCv/zDzIPQSM5WgzVGEbpjJ407/VJgfJ6ZcWymmEMNjIgZr 6FIuDCsOlZGa0XPQxbQpaalGOXemLZv4+nko5ls0LF2Siacw/FO04gIQol8Tk06COhbI ka/Q== X-Gm-Message-State: APzg51CDCpImrfUAOqOCJvap1KTmS3m3mFNDWh/raSovfjkRZjQdsn3L db9rM3LUqd1wUq7Hk+ePwfHwBzMugMQ= X-Google-Smtp-Source: ANB0VdYlvxsBDLLNbf4dpWuwkvCuWll/bhE5B3VdxQWLDxVK3i79lheTf2i6HHLlmX+Iz1L5iHcWkA== X-Received: by 2002:a24:61d2:: with SMTP id s201-v6mr6990328itc.22.1536023183007; Mon, 03 Sep 2018 18:06:23 -0700 (PDT) Received: from Maximus-IX-Hero.lede-router.local ([2601:446:4200:d870::c33]) by smtp.gmail.com with ESMTPSA id g205-v6sm7538623iof.69.2018.09.03.18.06.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Sep 2018 18:06:22 -0700 (PDT) From: Chris Blake To: u-boot@lists.denx.de Date: Mon, 3 Sep 2018 20:06:15 -0500 Message-Id: <1536023175-10682-3-git-send-email-chrisrblake93@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536023175-10682-1-git-send-email-chrisrblake93@gmail.com> References: <1536023175-10682-1-git-send-email-chrisrblake93@gmail.com> Cc: Chris Blake Subject: [U-Boot] [PATCH 2/2] watchdog: Add sunxi watchdog driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Based on the linux mainline driver, this adds support for the hardware watchdog timer found on some sunxi boards. Signed-off-by: Chris Blake --- common/board_f.c | 3 +- drivers/watchdog/Kconfig | 18 ++++++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/sunxi_wdt.c | 103 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 124 insertions(+), 1 deletion(-) create mode 100644 drivers/watchdog/sunxi_wdt.c diff --git a/common/board_f.c b/common/board_f.c index 88d7700..7b0d912 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -91,7 +91,8 @@ static int init_func_watchdog_init(void) (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ defined(CONFIG_DESIGNWARE_WATCHDOG) || \ - defined(CONFIG_IMX_WATCHDOG)) + defined(CONFIG_IMX_WATCHDOG) || \ + defined(CONFIG_SUNXI_WDT)) hw_watchdog_init(); puts(" Watchdog enabled\n"); # endif diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d545b3e..bd09dad 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -20,6 +20,24 @@ config BCM2835_WDT This provides basic infrastructure to support BCM2835/2836 watchdog hardware, with a max timeout of ~15secs. +config SUNXI_WDT + bool "SUNXI watchdog timer support" + select HW_WATCHDOG + help + Select this to enable the SUNXI watchdog timer. + +if SUNXI_WDT + +config SUNXI_WDT_TIMEOUT + int "SUNXI watchdog timeout setting" + default 10 + range 1 16 + depends on SUNXI_WDT + help + Adjust the timeout window for the SUNXI watchdog timer. + +endif + config OMAP_WATCHDOG bool "TI OMAP watchdog driver" depends on ARCH_OMAP2PLUS diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index f405f51..ce27bb5 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -23,3 +23,4 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o +obj-$(CONFIG_SUNXI_WDT) += sunxi_wdt.o diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c new file mode 100644 index 0000000..9d88b86 --- /dev/null +++ b/drivers/watchdog/sunxi_wdt.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2018 Chris Blake + * Roughly based on the mainline linux driver, sunxi_wdt.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include + +#define WDT_CTRL_RESTART (0x1 << 0) +#define WDT_CTRL_KEY (0x0a57 << 1) +#define WDT_MODE_EN (0x1 << 0) +#define WDT_TIMEOUT_MASK (0xf) + +struct sunxi_wdt_reg { + u32 wdt_ctrl; + u32 wdt_cfg; + u32 wdt_mode; + u32 wdt_timeout_shift; + u32 wdt_reset_mask; + u32 wdt_reset_val; +}; + +static const struct sunxi_wdt_reg sun4i_wdt_reg = { + .wdt_ctrl = 0x00, + .wdt_cfg = 0x04, + .wdt_mode = 0x04, + .wdt_timeout_shift = 3, + .wdt_reset_mask = 0x02, + .wdt_reset_val = 0x02, +}; + +static const struct sunxi_wdt_reg sun6i_dog_regs = { + .wdt_ctrl = 0x10, + .wdt_cfg = 0x14, + .wdt_mode = 0x18, + .wdt_timeout_shift = 4, + .wdt_reset_mask = 0x03, + .wdt_reset_val = 0x01, +}; + +static const int wdt_timeout_map[] = { + [1] = 0x1, /* 1s */ + [2] = 0x2, /* 2s */ + [3] = 0x3, /* 3s */ + [4] = 0x4, /* 4s */ + [5] = 0x5, /* 5s */ + [6] = 0x6, /* 6s */ + [8] = 0x7, /* 8s */ + [10] = 0x8, /* 10s */ + [12] = 0x9, /* 12s */ + [14] = 0xA, /* 14s */ + [16] = 0xB, /* 16s */ +}; + +#if defined(CONFIG_SUNXI_GEN_SUN6I) +static const struct sunxi_wdt_reg *regs = &sun6i_dog_regs; +#else +static const struct sunxi_wdt_reg *regs = &sun4i_dog_regs; +#endif + +static void *wdt_base = &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + +void hw_watchdog_reset(void) +{ + /* reload the watchdog */ + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, wdt_base + regs->wdt_ctrl); +} + +void hw_watchdog_disable(void) +{ + /* Reset WDT Config */ + writel(0, wdt_base + regs->wdt_mode); +} + +void hw_watchdog_init(void) +{ + const u32 timeout = CONFIG_SUNXI_WDT_TIMEOUT; + u32 reg; + + reg = readl(wdt_base + regs->wdt_mode); + reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift); + reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift; + writel(reg, wdt_base + regs->wdt_mode); + + hw_watchdog_reset(); + + /* Set system reset function */ + reg = readl(wdt_base + regs->wdt_cfg); + reg &= ~(regs->wdt_reset_mask); + reg |= regs->wdt_reset_val; + writel(reg, wdt_base + regs->wdt_cfg); + + /* Enable watchdog */ + reg = readl(wdt_base + regs->wdt_mode); + reg |= WDT_MODE_EN; + writel(reg, wdt_base + regs->wdt_mode); + }