From patchwork Thu Apr 26 15:05:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 905131 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40X0nt3wYnz9ry1 for ; Fri, 27 Apr 2018 01:08:50 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 46271C22147; Thu, 26 Apr 2018 15:07:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 42D7FC2215A; Thu, 26 Apr 2018 15:05:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8CE80C22150; Thu, 26 Apr 2018 15:05:39 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id C8934C2214A for ; Thu, 26 Apr 2018 15:05:35 +0000 (UTC) Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3QF54HD017535; Thu, 26 Apr 2018 17:05:35 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hj2m240uj-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 26 Apr 2018 17:05:35 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B62E934; Thu, 26 Apr 2018 15:05:34 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 900664F5D; Thu, 26 Apr 2018 15:05:34 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 26 Apr 2018 17:05:34 +0200 From: Patrice Chotard To: Jagan Teki Date: Thu, 26 Apr 2018 17:05:16 +0200 Message-ID: <1524755121-2077-7-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1524755121-2077-1-git-send-email-patrice.chotard@st.com> References: <1524755121-2077-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-26_06:, , signatures=0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v1 06/11] spi: stm32_qspi: Update mode management X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Christophe Kerello We face issue on Macronix/Spansion spi nors due to bad mode management. We solve these issues using following mode configurations: - read_cmd = CMD_READ_QUAD_OUTPUT_FAST => 1-1-4 - read_cmd = CMD_READ_DUAL_OUTPUT_FAST => 1-1-2 - write_cmd = CMD_QUAD_PAGE_PROGRAM => 1-1-4 - others commands => 1-1-1 Signed-off-by: Christophe Kerello Signed-off-by: Patrice Chotard --- drivers/spi/stm32_qspi.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 6b7232905bc8..46915194f034 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -156,6 +156,10 @@ enum STM32_QSPI_CCR_FMODE { /* default SCK frequency, unit: HZ */ #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000 +#define STM32_CMD_READ_DUAL_OUTPUT_FAST 0x3b +#define STM32_CMD_READ_QUAD_OUTPUT_FAST 0x6b +#define STM32_CMD_QUAD_PP 0x32 + struct stm32_qspi_platdata { u32 base; u32 memory_map; @@ -217,26 +221,28 @@ static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv) { unsigned int ccr_reg = 0; u8 imode, admode, dmode; - u32 mode = priv->mode; u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK); imode = STM32_QSPI_CCR_IMODE_ONE_LINE; admode = STM32_QSPI_CCR_ADMODE_ONE_LINE; - if (mode & SPI_RX_QUAD) { + /* + * Based on mtd spi framework, + * read_cmd = CMD_READ_QUAD_OUTPUT_FAST if (mode & SPI_RX_QUAD) + * read_cmd = CMD_READ_DUAL_OUTPUT_FAST if (mode & SPI_RX_DUAL) + * write_cmd = CMD_QUAD_PAGE_PROGRAM if (mode & SPI_TX_QUAD) + */ + switch (cmd) { + case STM32_CMD_READ_QUAD_OUTPUT_FAST: + case STM32_CMD_QUAD_PP: dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE; - if (mode & SPI_TX_QUAD) { - imode = STM32_QSPI_CCR_IMODE_FOUR_LINE; - admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE; - } - } else if (mode & SPI_RX_DUAL) { + break; + case STM32_CMD_READ_DUAL_OUTPUT_FAST: dmode = STM32_QSPI_CCR_DMODE_TWO_LINE; - if (mode & SPI_TX_DUAL) { - imode = STM32_QSPI_CCR_IMODE_TWO_LINE; - admode = STM32_QSPI_CCR_ADMODE_TWO_LINE; - } - } else { + break; + default: dmode = STM32_QSPI_CCR_DMODE_ONE_LINE; + break; } if (priv->command & CMD_HAS_DATA)