From patchwork Wed Apr 18 01:05:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 899807 X-Patchwork-Delegate: yamada.m@jp.panasonic.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40QkTt6jSVz9s1d for ; Wed, 18 Apr 2018 11:06:41 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1E827C21E90; Wed, 18 Apr 2018 01:06:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6D551C21DA1; Wed, 18 Apr 2018 01:06:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 09376C21DD4; Wed, 18 Apr 2018 01:05:46 +0000 (UTC) Received: from mx.socionext.com (mx.socionext.com [202.248.49.38]) by lists.denx.de (Postfix) with ESMTP id C82BBC21DA1 for ; Wed, 18 Apr 2018 01:05:45 +0000 (UTC) Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 18 Apr 2018 10:05:43 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 1524561851 for ; Wed, 18 Apr 2018 10:05:43 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 18 Apr 2018 10:05:42 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 723A11A0DEC; Wed, 18 Apr 2018 10:05:42 +0900 (JST) From: Kunihiko Hayashi To: u-boot@lists.denx.de Date: Wed, 18 Apr 2018 10:05:33 +0900 Message-Id: <1524013533-1719-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 X-Mailman-Approved-At: Wed, 18 Apr 2018 01:06:32 +0000 Subject: [U-Boot] [PATCH] clk: uniphier: add ethernet clock control support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add clock control for ethernet controller on each SoC. Signed-off-by: Kunihiko Hayashi --- drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index c852c78..0230a18 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -21,7 +21,10 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) ||\ defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) UNIPHIER_LD4_SYS_CLK_NAND(2), + UNIPHIER_CLK_GATE_SIMPLE(6, 0x2104, 12), /* ether (Pro4, PXs2) */ + UNIPHIER_CLK_GATE_SIMPLE(7, 0x2104, 5), /* ether-gb (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x2104, 10), /* stdmac */ + UNIPHIER_CLK_GATE_SIMPLE(10, 0x2260, 0), /* ether-phy (Pro4) */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ @@ -34,6 +37,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 6), /* ether */ UNIPHIER_CLK_GATE_SIMPLE(8, 0x210c, 8), /* stdmac */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14), /* usb30 (LD20) */ UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ @@ -45,6 +49,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { #if defined(CONFIG_ARCH_UNIPHIER_PXS3) UNIPHIER_LD11_SYS_CLK_NAND(2), + UNIPHIER_CLK_GATE_SIMPLE(6, 0x210c, 9), /* ether0 */ + UNIPHIER_CLK_GATE_SIMPLE(7, 0x210c, 10), /* ether1 */ UNIPHIER_CLK_GATE_SIMPLE(12, 0x210c, 4), /* usb30 (gio0) */ UNIPHIER_CLK_GATE_SIMPLE(13, 0x210c, 5), /* usb31-0 (gio1) */ UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 6), /* usb31-1 (gio1-1) */