From patchwork Mon Apr 16 08:13:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 898507 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40Ph4D2kHnz9s0b for ; Mon, 16 Apr 2018 18:14:20 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 19E65C21DB6; Mon, 16 Apr 2018 08:14:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D176FC21D9A; Mon, 16 Apr 2018 08:13:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C1F0BC21BE5; Mon, 16 Apr 2018 08:13:51 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 72B64C21C27 for ; Mon, 16 Apr 2018 08:13:51 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3G89X68014969; Mon, 16 Apr 2018 10:13:49 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hcptmrewa-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 16 Apr 2018 10:13:49 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 445BA42; Mon, 16 Apr 2018 08:13:48 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 27EF61603; Mon, 16 Apr 2018 08:13:48 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 16 Apr 2018 10:13:48 +0200 Received: from localhost (10.201.23.85) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 16 Apr 2018 10:13:47 +0200 From: Patrick Delaunay To: Date: Mon, 16 Apr 2018 10:13:22 +0200 Message-ID: <1523866404-10884-1-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-16_04:, , signatures=0 Cc: Tom Rini , Benjamin GAIGNARD Subject: [U-Boot] [PATCH v2 1/3] arm: psci: save context id for cpu_on PSCI command X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Save and use the 3rd parameter of PSCI CPU_ON request: context_id. The context_id parameter is only meaningful to the caller. U-Boot PSCI preserves a copy of the value passed in this parameter. Following wakeup from a powerdown state, U-BOOT PSCI places this value in R0 when it first enters the OS. NB: this context id is not (yet?) used by Linux but it is mandatory to be PSCI compliant. update armv7 psci functions: - psci_save_target_pc(): keep for backward compatibility with current platform (only save PC and force context id to 0) => should be removed when all platform migrate to the new API - psci_save(): new API to use by ARMv7 platform with PSCI, save pc (= entry_point_address) and context_id Signed-off-by: Patrick Delaunay Reviewed-by: Stephen Warren Reviewed-by: Masahiro Yamada --- Changes in v2: None arch/arm/cpu/armv7/psci-common.c | 14 ++++++++++++++ arch/arm/cpu/armv7/psci.S | 4 ++++ arch/arm/include/asm/psci.h | 4 +++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c index 8cb4107..73f986b 100644 --- a/arch/arm/cpu/armv7/psci-common.c +++ b/arch/arm/cpu/armv7/psci-common.c @@ -25,10 +25,19 @@ #include static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 }; +static u32 psci_context_id[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 }; void __secure psci_save_target_pc(int cpu, u32 pc) { psci_target_pc[cpu] = pc; + psci_context_id[cpu] = 0; + dsb(); +} + +void __secure psci_save(int cpu, u32 pc, u32 context_id) +{ + psci_target_pc[cpu] = pc; + psci_context_id[cpu] = context_id; dsb(); } @@ -37,3 +46,8 @@ u32 __secure psci_get_target_pc(int cpu) return psci_target_pc[cpu]; } +u32 __secure psci_get_context_id(int cpu) +{ + return psci_context_id[cpu]; +} + diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 95b962d..35fd955 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -327,6 +327,10 @@ ENTRY(psci_cpu_entry) bl _nonsec_init bl psci_get_cpu_id @ CPU ID => r0 + mov r2, r0 @ CPU ID => r2 + bl psci_get_context_id @ context id => r0 + mov r1, r0 @ context id => r1 + mov r0, r2 @ CPU ID => r0 bl psci_get_target_pc @ target PC => r0 b _do_nonsec_entry ENDPROC(psci_cpu_entry) diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index ac8b00d..b415241 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -93,9 +93,11 @@ #ifndef __ASSEMBLY__ #include -/* These 2 helper functions assume cpu < CONFIG_ARMV7_PSCI_NR_CPUS */ +/* These 4 helper functions assume cpu < CONFIG_ARMV7_PSCI_NR_CPUS */ u32 psci_get_target_pc(int cpu); +u32 psci_get_context_id(int cpu); void psci_save_target_pc(int cpu, u32 pc); +void psci_save(int cpu, u32 pc, u32 context_id); void psci_cpu_entry(void); u32 psci_get_cpu_id(void);