From patchwork Fri Apr 13 15:07:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan O'Donoghue X-Patchwork-Id: 897980 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="a3bmfcIJ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40N1NV5bHyz9s15 for ; Sat, 14 Apr 2018 01:07:38 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 71C63C21DAF; Fri, 13 Apr 2018 15:07:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0C7CAC21CB1; Fri, 13 Apr 2018 15:07:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DD1C2C21CB6; Fri, 13 Apr 2018 15:07:23 +0000 (UTC) Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) by lists.denx.de (Postfix) with ESMTPS id CD26AC21C2F for ; Fri, 13 Apr 2018 15:07:22 +0000 (UTC) Received: by mail-wr0-f195.google.com with SMTP id f7so2055821wrh.6 for ; Fri, 13 Apr 2018 08:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=iIF9MW1nQgz8EBPz3Hhdzx27U3TjQco17RsbDFhMihQ=; b=a3bmfcIJ2OlY2an0UYQW/t0ZEotz6mcvRJG4IfuXx65GbNMJ/N7aW0gwtKfQ3p8/sI qSlI4XbyHpw7uvgkrvcHi+Lk2QvW0kkIfTu/Q8FU9VhZjZjr6+mVjjbYtpYCRvyEhwU0 sDAlPJN1guW0DaVA0JLJlY7isasyc3SYJEzAU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=iIF9MW1nQgz8EBPz3Hhdzx27U3TjQco17RsbDFhMihQ=; b=RLFke95X0fQpSQ5X1n2BZ4QLG9ZzXzfH/T1dvKiQr/UJmjCYLQKREuD/aWnIihmF1q aUkzVKwVEZpVzKOzJ1slj5U+bffb9fSzFtO0BDclYlDmj65arHqHj3Ye31Aj8GjyWsL8 gmhWZZn5fOrBp2EjjeSEWOdm/lNVgO8S1beF/FoJ3kSErGrMZbR0bXLqIDt7ZEVVGFz0 /2bXIZGdxYk0YPAIZChcrm4DmA6QDkzkjJgCW4QQ/vBPEYdjklGv8eRQ2FtSdXWuLxB8 F8AlfuGPs4Z5yLi6PaGHSAwQzTmvauIUJUEhvMjVxATWwGW8qCa0PsbUpBUIogDoPwLq Pprw== X-Gm-Message-State: ALQs6tChqgB5fH1RfPnVaOzNVJi01rAL/8CqqqlwzRUvo5S2++bBZ+Nz fLo/KnkkclH9wOrTqUpTYKJh+9XvvJ4= X-Google-Smtp-Source: AIpwx499UMlxqrSIZ4rtUdpN7rBvJWLmXyGQBnHJrC4KaXL9Hw9MBYh/edUyVT6sg8iy2IFQnXgTiA== X-Received: by 10.80.163.196 with SMTP id t4mr20507282edb.202.1523632042296; Fri, 13 Apr 2018 08:07:22 -0700 (PDT) Received: from localhost.localdomain ([109.255.42.2]) by smtp.gmail.com with ESMTPSA id 27sm1953138edz.22.2018.04.13.08.07.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Apr 2018 08:07:21 -0700 (PDT) From: Bryan O'Donoghue To: U-Boot@lists.denx.de Date: Fri, 13 Apr 2018 16:07:20 +0100 Message-Id: <1523632040-12669-1-git-send-email-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [PATCH] bootm: Align cache flush begin address X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" commit b4d956f6bc0f ("bootm: Align cache flush end address correctly") aligns the end address of the cache flush operation to a cache-line size to ensure lower-layers in the code accept the range provided and flush. A similar action should be taken for the begin address of a cache flush operation. The load address may not be aligned to a cache-line boundary, so ensure the passed address is aligned. Signed-off-by: Bryan O'Donoghue Reported-by: Breno Matheus Lima Cc: Simon Glass --- common/bootm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/bootm.c b/common/bootm.c index adb1213..45d140c 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -447,7 +447,8 @@ static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end, bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); return err; } - flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN)); + flush_cache(ALIGN(load, ARCH_DMA_MINALIGN), + ALIGN(*load_end - load, ARCH_DMA_MINALIGN)); debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end); bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);