From patchwork Mon Mar 12 09:46:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 884373 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 400Cqg44Bdz9sNd for ; Mon, 12 Mar 2018 20:49:03 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 31BCBC21DA6; Mon, 12 Mar 2018 09:47:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 78C23C21DB3; Mon, 12 Mar 2018 09:46:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 51824C21DD9; Mon, 12 Mar 2018 09:46:41 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 25C41C21E08 for ; Mon, 12 Mar 2018 09:46:36 +0000 (UTC) Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w2C9i2EU006758; Mon, 12 Mar 2018 10:46:31 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2gm5q0rxw0-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 12 Mar 2018 10:46:31 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B541E31; Mon, 12 Mar 2018 09:46:30 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9D2CC24A0; Mon, 12 Mar 2018 09:46:30 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 12 Mar 2018 10:46:30 +0100 Received: from localhost (10.201.23.85) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 12 Mar 2018 10:46:29 +0100 From: Patrick Delaunay To: Date: Mon, 12 Mar 2018 10:46:06 +0100 Message-ID: <1520847978-24321-4-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520847978-24321-1-git-send-email-patrick.delaunay@st.com> References: <1520847978-24321-1-git-send-email-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-12_05:, , signatures=0 Cc: benjamin.gaignard@st.com Subject: [U-Boot] [PATCH v2 03/15] arm: armv7: solve issue for timer_rate_hz in arch timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The current value timer_rate_hz causes a problem with function timer_get_us() from lib time and then an issue with readx_poll_timeout() function. With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK the weak functions in lib timer can be used: - get_timer() - __udelay() So the specific function in this file are removed. Signed-off-by: Patrick Delaunay --- this patch avoid issue in driver with readl_poll_timeout() Following source code has been used to demonstrate the issue (with CONFIG_SYS_HZ_CLOCK = 64 MHz) printf("Tick= %llx us=%lx boot us=%lx\n", get_ticks(), timer_get_us(), timer_get_boot_us()); mdelay(1000); printf("Tick= %llx us=%lx boot us=%lx\n", get_ticks(), timer_get_us(), timer_get_boot_us()); Result: Tick= 36fad40 us=35b0f45f boot us=dbeb8 Tick= 743b21e us=7181c02e boot us=1d0ecb => 1000ms : 0x1d0ecb-0xdbeb8 = 0xF5013 for timer_get_boot_us = 1000000 us => timer_get_boot_us is OK => 1000ms : 0x7181c02e-0x35b0f45f = 0x3BD0CBCF = 1.000.000.000 us for timer_get_us() which gives a invalid value (based on CONFIG_SYS_HZ and get_tbclk()) This patch resolves the issue. Changes in v2: None arch/arm/cpu/armv7/arch_timer.c | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index 30915d2..545c518 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -17,7 +17,7 @@ int timer_init(void) gd->arch.tbl = 0; gd->arch.tbu = 0; - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ; + gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; return 0; } @@ -34,27 +34,9 @@ unsigned long long get_ticks(void) } -ulong get_timer(ulong base) -{ - return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base; -} - ulong timer_get_boot_us(void) { - return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000)); -} - -void __udelay(unsigned long usec) -{ - unsigned long long endtime; - - endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz, - 1000UL); - - endtime += get_ticks(); - - while (get_ticks() < endtime) - ; + return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / 1000000); } ulong get_tbclk(void)