From patchwork Thu Mar 8 10:00:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Calvin Johnson X-Patchwork-Id: 883030 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxmJD09b6z9sh5 for ; Thu, 8 Mar 2018 21:01:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 91F89C21F05; Thu, 8 Mar 2018 10:01:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C7BC6C21FDE; Thu, 8 Mar 2018 09:55:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6FED5C21F97; Thu, 8 Mar 2018 09:54:16 +0000 (UTC) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lists.denx.de (Postfix) with ESMTPS id 81344C21F4E for ; Thu, 8 Mar 2018 09:54:12 +0000 (UTC) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5CF431A019E; Thu, 8 Mar 2018 10:54:12 +0100 (CET) Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 289851A019C; Thu, 8 Mar 2018 10:54:12 +0100 (CET) Received: from ab-OptiPlex-7010.ap.freescale.net (ab-OptiPlex-7010.ap.freescale.net [10.207.242.207]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 7D71934F; Thu, 8 Mar 2018 15:24:11 +0530 (IST) From: Calvin Johnson To: u-boot@lists.denx.de, Joe Hershberger Date: Thu, 8 Mar 2018 15:30:32 +0530 Message-Id: <1520503236-5945-11-git-send-email-calvin.johnson@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520503236-5945-1-git-send-email-calvin.johnson@nxp.com> References: <1520503236-5945-1-git-send-email-calvin.johnson@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Cc: Anjaneyulu Jagarlmudi Subject: [U-Boot] [PATCH v4 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" SoC specific PFE macros are defined and structure ccsr_scfg is updated with members defined for PFE. Signed-off-by: Calvin Johnson Signed-off-by: Anjaneyulu Jagarlmudi Acked-by: Joe Hershberger --- Changes in v4: None Changes in v3: -Use BIT macro wherever applicable Changes in v2: None .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 38 ++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index b195005..d6f0c5b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -395,6 +395,21 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 +/* RGMIIPCR bit definitions*/ +#define SCFG_RGMIIPCR_EN_AUTO BIT(3) +#define SCFG_RGMIIPCR_SETSP_1000M BIT(2) +#define SCFG_RGMIIPCR_SETSP_100M 0 +#define SCFG_RGMIIPCR_SETSP_10M BIT(1) +#define SCFG_RGMIIPCR_SETFD BIT(0) + +/* PFEASBCR bit definitions */ +#define SCFG_PFEASBCR_ARCACHE0 BIT(31) +#define SCFG_PFEASBCR_AWCACHE0 BIT(30) +#define SCFG_PFEASBCR_ARCACHE1 BIT(29) +#define SCFG_PFEASBCR_AWCACHE1 BIT(28) +#define SCFG_PFEASBCR_ARSNP BIT(27) +#define SCFG_PFEASBCR_AWSNP BIT(26) + /* Supplemental Configuration Unit */ struct ccsr_scfg { u8 res_000[0x100-0x000]; @@ -412,7 +427,12 @@ struct ccsr_scfg { u8 res_140[0x158-0x140]; u32 altcbar; u32 qspi_cfg; - u8 res_160[0x180-0x160]; + u8 res_160[0x164 - 0x160]; + u32 wr_qos1; + u32 wr_qos2; + u32 rd_qos1; + u32 rd_qos2; + u8 res_174[0x180 - 0x174]; u32 dmamcr; u8 res_184[0x188-0x184]; u32 gic_align; @@ -443,7 +463,21 @@ struct ccsr_scfg { u32 usb_refclk_selcr1; u32 usb_refclk_selcr2; u32 usb_refclk_selcr3; - u8 res_424[0x600-0x424]; + u8 res_424[0x434 - 0x424]; + u32 rgmiipcr; + u32 res_438; + u32 rgmiipsr; + u32 pfepfcssr1; + u32 pfeintencr1; + u32 pfepfcssr2; + u32 pfeintencr2; + u32 pfeerrcr; + u32 pfeeerrintencr; + u32 pfeasbcr; + u32 pfebsbcr; + u8 res_460[0x484 - 0x460]; + u32 mdioselcr; + u8 res_468[0x600 - 0x488]; u32 scratchrw[4]; u8 res_610[0x680-0x610]; u32 corebcr;