From patchwork Thu Mar 8 10:00:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Calvin Johnson X-Patchwork-Id: 883032 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zxmJv666Jz9sh5 for ; Thu, 8 Mar 2018 21:02:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 80986C21F67; Thu, 8 Mar 2018 10:00:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B9035C21F67; Thu, 8 Mar 2018 09:54:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1D869C21E5B; Thu, 8 Mar 2018 09:54:15 +0000 (UTC) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lists.denx.de (Postfix) with ESMTPS id 1CD96C21F05 for ; Thu, 8 Mar 2018 09:54:11 +0000 (UTC) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id EE06820007D; Thu, 8 Mar 2018 10:54:10 +0100 (CET) Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 8589020004A; Thu, 8 Mar 2018 10:54:10 +0100 (CET) Received: from ab-OptiPlex-7010.ap.freescale.net (ab-OptiPlex-7010.ap.freescale.net [10.207.242.207]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id C86C834F; Thu, 8 Mar 2018 15:24:09 +0530 (IST) From: Calvin Johnson To: u-boot@lists.denx.de, Joe Hershberger Date: Thu, 8 Mar 2018 15:30:31 +0530 Message-Id: <1520503236-5945-10-git-send-email-calvin.johnson@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1520503236-5945-1-git-send-email-calvin.johnson@nxp.com> References: <1520503236-5945-1-git-send-email-calvin.johnson@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Cc: Bhaskar Upadhaya , Anjaneyulu Jagarlmudi Subject: [U-Boot] [PATCH v4 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch enables ethernet support for ls1012a2g5rdb. Signed-off-by: Calvin Johnson Signed-off-by: Bhaskar Upadhaya Acked-by: Joe Hershberger --- Changes in v4: None Changes in v3: -Update Kconfig -Update header file location to include/net/pfe_eth -Prefix CONFIG_PFE_ to appropriate macros -Indent properly Changes in v2: -New patch added to series to enable ethernet support for ls1012a2g5rdb board/freescale/ls1012ardb/Kconfig | 30 +++++++++++++++++++++++++ board/freescale/ls1012ardb/eth.c | 45 +++++++++++++++++++++++++++++++------- 2 files changed, 67 insertions(+), 8 deletions(-) diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index af35a01..493d477 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -59,6 +59,36 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1012a2g5rdb" +if FSL_PFE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select PHYLIB + imply CONFIG_PHYLIB_10G + imply CONFIG_PHY_AQUANTIA + +config SYS_LS_PFE_FW_ADDR + hex "Flash address of PFE firmware" + default 0x40a00000 + +config DDR_PFE_PHYS_BASEADDR + hex "PFE DDR physical base address" + default 0x03800000 + +config DDR_PFE_BASEADDR + hex "PFE DDR base address" + default 0x83800000 + +config PFE_EMAC1_PHY_ADDR + hex "PFE DDR base address" + default 0x2 + +config PFE_EMAC2_PHY_ADDR + hex "PFE DDR base address" + default 0x1 + +endif + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index e6379a3..8e6cd0a 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -26,6 +26,7 @@ static inline void ls1012ardb_reset_phy(void) { +#ifdef CONFIG_TARGET_LS1012ARDB /* Through reset IO expander reset both RGMII and SGMII PHYs */ i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK); @@ -34,6 +35,7 @@ static inline void ls1012ardb_reset_phy(void) mdelay(10); i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF); mdelay(50); +#endif } int pfe_eth_board_init(struct udevice *dev) @@ -42,6 +44,11 @@ int pfe_eth_board_init(struct udevice *dev) struct mii_dev *bus; struct pfe_mdio_info mac_mdio_info; struct pfe_eth_dev *priv = dev_get_priv(dev); + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + int srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; if (!init_done) { ls1012ardb_reset_phy(); @@ -59,14 +66,36 @@ int pfe_eth_board_init(struct udevice *dev) pfe_set_mdio(priv->gemac_port, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME)); - if (!priv->gemac_port) { - /* MAC1 */ - pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR, - PHY_INTERFACE_MODE_SGMII); - } else { - /* MAC2 */ - pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR, - PHY_INTERFACE_MODE_RGMII_TXID); + switch (srds_s1) { + case 0x3508: + if (!priv->gemac_port) { + /* MAC1 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII); + } else { + /* MAC2 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_RGMII_TXID); + } + break; + case 0x2208: + if (!priv->gemac_port) { + /* MAC1 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC1_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII_2500); + } else { + /* MAC2 */ + pfe_set_phy_address_mode(priv->gemac_port, + CONFIG_PFE_EMAC2_PHY_ADDR, + PHY_INTERFACE_MODE_SGMII_2500); + } + break; + default: + printf("unsupported SerDes PRCTL= %d\n", srds_s1); + break; } return 0; }