From patchwork Thu Feb 15 14:17:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Calvin Johnson X-Patchwork-Id: 873878 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zhyyW3fVvz9sRm for ; Fri, 16 Feb 2018 01:17:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BA394C22158; Thu, 15 Feb 2018 14:15:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 05543C22185; Thu, 15 Feb 2018 14:12:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8C8B8C22158; Thu, 15 Feb 2018 14:11:06 +0000 (UTC) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lists.denx.de (Postfix) with ESMTPS id 20BA5C21D74 for ; Thu, 15 Feb 2018 14:11:03 +0000 (UTC) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id F00E020001B; Thu, 15 Feb 2018 15:11:02 +0100 (CET) Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id BB2442000BA; Thu, 15 Feb 2018 15:11:02 +0100 (CET) Received: from ab-OptiPlex-7010.ap.freescale.net (unknown [10.207.242.207]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 0B58F33F; Thu, 15 Feb 2018 19:41:02 +0530 (IST) From: Calvin Johnson To: u-boot@lists.denx.de Date: Thu, 15 Feb 2018 19:47:09 +0530 Message-Id: <1518704240-27155-3-git-send-email-calvin.johnson@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518704240-27155-1-git-send-email-calvin.johnson@nxp.com> References: <1518704240-27155-1-git-send-email-calvin.johnson@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Cc: Pratiyush Srivastava , anji.jagarlmudi@nxp.com, joe.hershberger@ni.com Subject: [U-Boot] [PATCH v2 02/13] armv8: fsl-layerscape: Add support of GPIO structure X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Prabhakar Kushwaha Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava Signed-off-by: Prabhakar Kushwaha Acked-by: Joe Hershberger --- Changes in v2: None --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 1ff5cac..b195005 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -82,6 +82,11 @@ #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) +#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) +#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) +#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) + #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) @@ -591,6 +596,16 @@ struct ccsr_serdes { u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) #define SMMU_SCR1 (SMMU_BASE + 0x4)