diff mbox series

[U-Boot,v2,02/13] armv8: fsl-layerscape: Add support of GPIO structure

Message ID 1518704240-27155-3-git-send-email-calvin.johnson@nxp.com
State Changes Requested
Delegated to: Joe Hershberger
Headers show
Series LS1012A PFE driver patch series | expand

Commit Message

Calvin Johnson Feb. 15, 2018, 2:17 p.m. UTC 
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Layerscape Gen2 SoC supports GPIO registers to control GPIO
signals. Adding support of GPIO structure to access GPIO
registers.

Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes in v2: None
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Joe Hershberger Feb. 27, 2018, 5:01 p.m. UTC | #1 
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
>
> Layerscape Gen2 SoC supports GPIO registers to control GPIO
> signals. Adding support of GPIO structure to access GPIO
> registers.
>
> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1ff5cac..b195005 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -82,6 +82,11 @@ 
 #define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
 #define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
 
+#define GPIO1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1300000)
+#define GPIO2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1310000)
+#define GPIO3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1320000)
+#define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1330000)
+
 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
 
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
@@ -591,6 +596,16 @@  struct ccsr_serdes {
 	u8	res_19a0[0x2000-0x19a0];	/* from 0x19a0 to 0x1fff */
 };
 
+struct ccsr_gpio {
+	u32	gpdir;
+	u32	gpodr;
+	u32	gpdat;
+	u32	gpier;
+	u32	gpimr;
+	u32	gpicr;
+	u32	gpibe;
+};
+
 /* MMU 500 */
 #define SMMU_SCR0			(SMMU_BASE + 0x0)
 #define SMMU_SCR1			(SMMU_BASE + 0x4)