From patchwork Fri Feb 9 12:09:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 871369 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zdDWM45Lpz9s72 for ; Fri, 9 Feb 2018 23:14:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id AD98AC21C4F; Fri, 9 Feb 2018 12:11:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B12E8C21E13; Fri, 9 Feb 2018 12:10:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 556DFC21D75; Fri, 9 Feb 2018 12:10:07 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 39B76C21D9F for ; Fri, 9 Feb 2018 12:10:06 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w19C9Zjt018884; Fri, 9 Feb 2018 13:10:05 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2fw3qx7nr9-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 09 Feb 2018 13:10:05 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8F04331; Fri, 9 Feb 2018 12:10:04 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 72E481330; Fri, 9 Feb 2018 12:10:04 +0000 (GMT) Received: from localhost (10.75.127.48) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 9 Feb 2018 13:10:02 +0100 From: To: , , , Date: Fri, 9 Feb 2018 13:09:55 +0100 Message-ID: <1518178197-32699-4-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518178197-32699-1-git-send-email-patrice.chotard@st.com> References: <1518178197-32699-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-02-09_06:, , signatures=0 Subject: [U-Boot] [PATCH v2 3/5] arch-stm32: Factorize stm32.h for STM32F4 and F7 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard For STM32F4 and F7 SoCx family, a specific stm32.h file exists. Some common defines are duplicated or even unused in each of these stm32.h. Factorize all common definition in arch/arm/include/asm/stm32f.h and keep specific definitions in each arch/arm/include/asm/arch-stm32fx/stm32.h. Signed-off-by: Patrice Chotard --- v2: _ create arch/arm/include/asm/arch-stm32 directory and move stm32f.h in it. arch/arm/include/asm/arch-stm32/stm32f.h | 22 +++++++++++++++ arch/arm/include/asm/arch-stm32f4/stm32.h | 14 ++-------- arch/arm/include/asm/arch-stm32f7/stm32.h | 45 +------------------------------ drivers/mtd/stm32_flash.c | 2 +- 4 files changed, 26 insertions(+), 57 deletions(-) create mode 100644 arch/arm/include/asm/arch-stm32/stm32f.h diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h new file mode 100644 index 000000000000..7bea20b4d06a --- /dev/null +++ b/arch/arm/include/asm/arch-stm32/stm32f.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_STM32F_H +#define _ASM_ARCH_STM32F_H + +#define STM32_PERIPH_BASE 0x40000000UL + +#define STM32_APB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) +#define STM32_AHB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) + +#define STM32_SYSCFG_BASE (STM32_APB2_PERIPH_BASE + 0x3800) +#define STM32_FLASH_CNTL_BASE (STM32_AHB1_PERIPH_BASE + 0x3C00) + +void stm32_flash_latency_cfg(int latency); + +#endif /* _ASM_ARCH_STM32F_H */ + diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 763b18cb5412..903931243c2c 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -11,17 +11,12 @@ #ifndef _MACH_STM32_H_ #define _MACH_STM32_H_ +#include + /* * Peripheral memory map */ #define STM32_SYSMEM_BASE 0x1FFF0000 -#define STM32_PERIPH_BASE 0x40000000 -#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) -#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) -#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) -#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000) - -#define STM32_BUS_MASK 0xFFFF0000 /* * Register maps @@ -37,15 +32,10 @@ struct stm32_u_id_regs { */ #define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) #define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) - -#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00) - static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { [0 ... 3] = 16 * 1024, [4] = 64 * 1024, [5 ... 11] = 128 * 1024 }; -void stm32_flash_latency_cfg(int latency); - #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index 40df89142608..c1f1ba2175e3 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -8,46 +8,7 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -/* STM32F746 */ -#define ITCM_FLASH_BASE 0x00200000UL -#define AXIM_FLASH_BASE 0x08000000UL - -#define ITCM_SRAM_BASE 0x00000000UL -#define DTCM_SRAM_BASE 0x20000000UL -#define SRAM1_BASE 0x20010000UL -#define SRAM2_BASE 0x2004C000UL - -#define PERIPH_BASE 0x40000000UL - -#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) -#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000) -#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000) - -#define USART2_BASE (APB1_PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1_PERIPH_BASE + 0x4800) -#define PWR_BASE (APB1_PERIPH_BASE + 0x7000) - -#define USART1_BASE (APB2_PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2_PERIPH_BASE + 0x1400) -#define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800) - -#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000) -#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400) -#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800) -#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00) -#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000) -#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400) -#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800) -#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00) -#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000) -#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400) -#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800) -#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00) - - -#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x40000140) +#include static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { [0 ... 3] = 32 * 1024, @@ -55,8 +16,4 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { [5 ... 7] = 256 * 1024 }; -#define STM32_BUS_MASK GENMASK(31, 16) - -void stm32_flash_latency_cfg(int latency); - #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c index 472499d83c3b..a82814272e21 100644 --- a/drivers/mtd/stm32_flash.c +++ b/drivers/mtd/stm32_flash.c @@ -12,7 +12,7 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -#define STM32_FLASH ((struct stm32_flash_regs *)FLASH_CNTL_BASE) +#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_CNTL_BASE) void stm32_flash_latency_cfg(int latency) {