| Message ID | 1517156391-11353-4-git-send-email-jagan@amarulasolutions.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | musb: sunxi: Add OTG-Peripheral support for Allwineer H3/H5/A64 | expand |
On 01/28/2018 05:19 PM, Jagan Teki wrote: > From: Chen-Yu Tsai <wens@csie.org> > > On the new chips such as H3, H5, and A64, the USB OTG controller is > paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, > the USB PHY index count has to be reworked to start from this pair. > > This patch reworks the USB clock gate and reset indices, and how the > USB host is mapped to a USB phy, for the newer chips. The ifdeffery is awful. The driver is DT capable, do why don't you detect the block type / soc type from DT and handle this dynamically instead of adding ifdefs ? > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > Reviewed-by: Jagan Teki <jagan@openedev.com> > [jagan: remove 3/8] from commit header] > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > Cc: Marek Vasut <marex@denx.de> > --- > arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 30 +++++++++++++-------------- > drivers/usb/host/ehci-sunxi.c | 9 +++++++- > drivers/usb/host/ohci-sunxi.c | 9 +++++++- > 3 files changed, 30 insertions(+), 18 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > index d328df9..2c82d0a 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h > @@ -270,17 +270,18 @@ struct sunxi_ccm_reg { > #define AXI_GATE_OFFSET_DRAM 0 > > /* ahb_gate0 offsets */ > +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) > +#define AHB_GATE_OFFSET_USB_OHCI3 31 > +#define AHB_GATE_OFFSET_USB_OHCI2 30 > +#define AHB_GATE_OFFSET_USB_OHCI1 29 > +#define AHB_GATE_OFFSET_USB_OHCI0 28 > +#define AHB_GATE_OFFSET_USB_EHCI3 27 > +#define AHB_GATE_OFFSET_USB_EHCI2 26 > +#define AHB_GATE_OFFSET_USB_EHCI1 25 > +#define AHB_GATE_OFFSET_USB_EHCI0 24 > +#else > #define AHB_GATE_OFFSET_USB_OHCI1 30 > #define AHB_GATE_OFFSET_USB_OHCI0 29 > -#ifdef CONFIG_MACH_SUNXI_H3_H5 > -/* > - * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call > - * them 0 - 2 like they were called on older SoCs. > - */ > -#define AHB_GATE_OFFSET_USB_EHCI2 27 > -#define AHB_GATE_OFFSET_USB_EHCI1 26 > -#define AHB_GATE_OFFSET_USB_EHCI0 25 > -#else > #define AHB_GATE_OFFSET_USB_EHCI1 27 > #define AHB_GATE_OFFSET_USB_EHCI0 26 > #endif > @@ -339,13 +340,10 @@ struct sunxi_ccm_reg { > #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) > #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) > #ifdef CONFIG_MACH_SUNXI_H3_H5 > -/* > - * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call > - * them 0 - 2 like they were called on older SoCs. > - */ > -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) > -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) > -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) > +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) > +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) > +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) > +#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) > #else > #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) > #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) > diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c > index 6ecb7c4..f40228e 100644 > --- a/drivers/usb/host/ehci-sunxi.c > +++ b/drivers/usb/host/ehci-sunxi.c > @@ -48,10 +48,17 @@ static int ehci_usb_probe(struct udevice *dev) > #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) > extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; > #endif > +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) > + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ > + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; > +#else > priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; > +#endif > priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; > extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; > - priv->phy_index++; /* Non otg phys start at 1 */ > +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) > + priv->phy_index++; /* older chips do not have EHCI with OTG */ > +#endif > > setbits_le32(&ccm->ahb_gate0, > priv->ahb_gate_mask | extra_ahb_gate_mask); > diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c > index 133774f..4b8a403 100644 > --- a/drivers/usb/host/ohci-sunxi.c > +++ b/drivers/usb/host/ohci-sunxi.c > @@ -51,11 +51,18 @@ static int ohci_usb_probe(struct udevice *dev) > extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; > #endif > priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; > +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) > + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ > + priv->phy_index = ((uintptr_t)regs - (SUNXI_USB0_BASE + 0x400)) / BASE_DIST; > +#else > priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; > +#endif > priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; > extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; > priv->usb_gate_mask <<= priv->phy_index; > - priv->phy_index++; /* Non otg phys start at 1 */ > +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) > + priv->phy_index++; /* older chips do not have OHCI with OTG */ > +#endif > > setbits_le32(&ccm->ahb_gate0, > priv->ahb_gate_mask | extra_ahb_gate_mask); >
On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut <marex@denx.de> wrote: > On 01/28/2018 05:19 PM, Jagan Teki wrote: >> From: Chen-Yu Tsai <wens@csie.org> >> >> On the new chips such as H3, H5, and A64, the USB OTG controller is >> paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, >> the USB PHY index count has to be reworked to start from this pair. >> >> This patch reworks the USB clock gate and reset indices, and how the >> USB host is mapped to a USB phy, for the newer chips. > > The ifdeffery is awful. The driver is DT capable, do why don't you > detect the block type / soc type from DT and handle this dynamically > instead of adding ifdefs ? Though this driver is DT capable phy, reset, clock and other still need to have have it. till now we are relying on ifdef's to move feature to work first.
On 01/28/2018 07:20 PM, Jagan Teki wrote: > On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut <marex@denx.de> wrote: >> On 01/28/2018 05:19 PM, Jagan Teki wrote: >>> From: Chen-Yu Tsai <wens@csie.org> >>> >>> On the new chips such as H3, H5, and A64, the USB OTG controller is >>> paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, >>> the USB PHY index count has to be reworked to start from this pair. >>> >>> This patch reworks the USB clock gate and reset indices, and how the >>> USB host is mapped to a USB phy, for the newer chips. >> >> The ifdeffery is awful. The driver is DT capable, do why don't you >> detect the block type / soc type from DT and handle this dynamically >> instead of adding ifdefs ? > > Though this driver is DT capable phy, reset, clock and other still > need to have have it. till now we are relying on ifdef's to move > feature to work first. This statement makes no sense, just use the DT compatible to discern the block type and get rid of statements like this: +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; +#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif You can associate data with each DT compatible in the struct udevice_id, so this should be rather trivial change _without_ adding any ifdefs.
On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut <marex@denx.de> wrote: > On 01/28/2018 07:20 PM, Jagan Teki wrote: >> On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut <marex@denx.de> wrote: >>> On 01/28/2018 05:19 PM, Jagan Teki wrote: >>>> From: Chen-Yu Tsai <wens@csie.org> >>>> >>>> On the new chips such as H3, H5, and A64, the USB OTG controller is >>>> paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, >>>> the USB PHY index count has to be reworked to start from this pair. >>>> >>>> This patch reworks the USB clock gate and reset indices, and how the >>>> USB host is mapped to a USB phy, for the newer chips. >>> >>> The ifdeffery is awful. The driver is DT capable, do why don't you >>> detect the block type / soc type from DT and handle this dynamically >>> instead of adding ifdefs ? >> >> Though this driver is DT capable phy, reset, clock and other still >> need to have have it. till now we are relying on ifdef's to move >> feature to work first. > > This statement makes no sense, just use the DT compatible to discern the > block type and get rid of statements like this: > > +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) > + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ > + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; > +#else > priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; > +#endif if you read it previous comment clearly for "phy, reset, clock" writes it may not possible and true for above ifdef.
On 01/28/2018 07:29 PM, Jagan Teki wrote: > On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut <marex@denx.de> wrote: >> On 01/28/2018 07:20 PM, Jagan Teki wrote: >>> On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut <marex@denx.de> wrote: >>>> On 01/28/2018 05:19 PM, Jagan Teki wrote: >>>>> From: Chen-Yu Tsai <wens@csie.org> >>>>> >>>>> On the new chips such as H3, H5, and A64, the USB OTG controller is >>>>> paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, >>>>> the USB PHY index count has to be reworked to start from this pair. >>>>> >>>>> This patch reworks the USB clock gate and reset indices, and how the >>>>> USB host is mapped to a USB phy, for the newer chips. >>>> >>>> The ifdeffery is awful. The driver is DT capable, do why don't you >>>> detect the block type / soc type from DT and handle this dynamically >>>> instead of adding ifdefs ? >>> >>> Though this driver is DT capable phy, reset, clock and other still >>> need to have have it. till now we are relying on ifdef's to move >>> feature to work first. > >> >> This statement makes no sense, just use the DT compatible to discern the >> block type and get rid of statements like this: >> >> +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) >> + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ >> + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; >> +#else >> priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; >> +#endif > > if you read it previous comment clearly for "phy, reset, clock" writes > it may not possible and true for above ifdef. I only see if (platform is foo or bar) set phy_index to something else set it to something else, therefore I think the comment about 'phy, reset, clock' is irrelevant. You can very well add ie. { .compatible = "allwinner,sun5i-a13-ohci", .data = TYPE_FOO }, And then do if (dev_get_driver_data(...) == TYPE_FOO) priv->phy_index = bar; else priv->.......; If you think this is not possible, please do explain why in detail.
On 01/28/2018 07:40 PM, Marek Vasut wrote: > On 01/28/2018 07:29 PM, Jagan Teki wrote: >> On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut <marex@denx.de> wrote: >>> On 01/28/2018 07:20 PM, Jagan Teki wrote: >>>> On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut <marex@denx.de> wrote: >>>>> On 01/28/2018 05:19 PM, Jagan Teki wrote: >>>>>> From: Chen-Yu Tsai <wens@csie.org> >>>>>> >>>>>> On the new chips such as H3, H5, and A64, the USB OTG controller is >>>>>> paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, >>>>>> the USB PHY index count has to be reworked to start from this pair. >>>>>> >>>>>> This patch reworks the USB clock gate and reset indices, and how the >>>>>> USB host is mapped to a USB phy, for the newer chips. >>>>> >>>>> The ifdeffery is awful. The driver is DT capable, do why don't you >>>>> detect the block type / soc type from DT and handle this dynamically >>>>> instead of adding ifdefs ? >>>> >>>> Though this driver is DT capable phy, reset, clock and other still >>>> need to have have it. till now we are relying on ifdef's to move >>>> feature to work first. >> >>> >>> This statement makes no sense, just use the DT compatible to discern the >>> block type and get rid of statements like this: >>> >>> +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) >>> + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ >>> + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; >>> +#else >>> priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; >>> +#endif >> >> if you read it previous comment clearly for "phy, reset, clock" writes >> it may not possible and true for above ifdef. > > I only see if (platform is foo or bar) set phy_index to something else > set it to something else, therefore I think the comment about 'phy, > reset, clock' is irrelevant. > > You can very well add ie. > { .compatible = "allwinner,sun5i-a13-ohci", .data = TYPE_FOO }, > > And then do > > if (dev_get_driver_data(...) == TYPE_FOO) > priv->phy_index = bar; > else > priv->.......; > > If you think this is not possible, please do explain why in detail. Can I expect a new patchset using DT properly ?
On Mon, Jan 29, 2018 at 10:04 PM, Marek Vasut <marex@denx.de> wrote: > On 01/28/2018 07:40 PM, Marek Vasut wrote: >> On 01/28/2018 07:29 PM, Jagan Teki wrote: >>> On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut <marex@denx.de> wrote: >>>> On 01/28/2018 07:20 PM, Jagan Teki wrote: >>>>> On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut <marex@denx.de> wrote: >>>>>> On 01/28/2018 05:19 PM, Jagan Teki wrote: >>>>>>> From: Chen-Yu Tsai <wens@csie.org> >>>>>>> >>>>>>> On the new chips such as H3, H5, and A64, the USB OTG controller is >>>>>>> paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, >>>>>>> the USB PHY index count has to be reworked to start from this pair. >>>>>>> >>>>>>> This patch reworks the USB clock gate and reset indices, and how the >>>>>>> USB host is mapped to a USB phy, for the newer chips. >>>>>> >>>>>> The ifdeffery is awful. The driver is DT capable, do why don't you >>>>>> detect the block type / soc type from DT and handle this dynamically >>>>>> instead of adding ifdefs ? >>>>> >>>>> Though this driver is DT capable phy, reset, clock and other still >>>>> need to have have it. till now we are relying on ifdef's to move >>>>> feature to work first. >>> >>>> >>>> This statement makes no sense, just use the DT compatible to discern the >>>> block type and get rid of statements like this: >>>> >>>> +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) >>>> + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ >>>> + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; >>>> +#else >>>> priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; >>>> +#endif >>> >>> if you read it previous comment clearly for "phy, reset, clock" writes >>> it may not possible and true for above ifdef. >> >> I only see if (platform is foo or bar) set phy_index to something else >> set it to something else, therefore I think the comment about 'phy, >> reset, clock' is irrelevant. >> >> You can very well add ie. >> { .compatible = "allwinner,sun5i-a13-ohci", .data = TYPE_FOO }, >> >> And then do >> >> if (dev_get_driver_data(...) == TYPE_FOO) >> priv->phy_index = bar; >> else >> priv->.......; >> >> If you think this is not possible, please do explain why in detail. > > Can I expect a new patchset using DT properly ? Yes Marek, I'm working on infact I'm trying to get these SOC's specs out from musb and writing phy driver for that matter.
On 01/29/2018 05:56 PM, Jagan Teki wrote: > On Mon, Jan 29, 2018 at 10:04 PM, Marek Vasut <marex@denx.de> wrote: >> On 01/28/2018 07:40 PM, Marek Vasut wrote: >>> On 01/28/2018 07:29 PM, Jagan Teki wrote: >>>> On Sun, Jan 28, 2018 at 11:55 PM, Marek Vasut <marex@denx.de> wrote: >>>>> On 01/28/2018 07:20 PM, Jagan Teki wrote: >>>>>> On Sun, Jan 28, 2018 at 10:01 PM, Marek Vasut <marex@denx.de> wrote: >>>>>>> On 01/28/2018 05:19 PM, Jagan Teki wrote: >>>>>>>> From: Chen-Yu Tsai <wens@csie.org> >>>>>>>> >>>>>>>> On the new chips such as H3, H5, and A64, the USB OTG controller is >>>>>>>> paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts, >>>>>>>> the USB PHY index count has to be reworked to start from this pair. >>>>>>>> >>>>>>>> This patch reworks the USB clock gate and reset indices, and how the >>>>>>>> USB host is mapped to a USB phy, for the newer chips. >>>>>>> >>>>>>> The ifdeffery is awful. The driver is DT capable, do why don't you >>>>>>> detect the block type / soc type from DT and handle this dynamically >>>>>>> instead of adding ifdefs ? >>>>>> >>>>>> Though this driver is DT capable phy, reset, clock and other still >>>>>> need to have have it. till now we are relying on ifdef's to move >>>>>> feature to work first. >>>> >>>>> >>>>> This statement makes no sense, just use the DT compatible to discern the >>>>> block type and get rid of statements like this: >>>>> >>>>> +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) >>>>> + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ >>>>> + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; >>>>> +#else >>>>> priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; >>>>> +#endif >>>> >>>> if you read it previous comment clearly for "phy, reset, clock" writes >>>> it may not possible and true for above ifdef. >>> >>> I only see if (platform is foo or bar) set phy_index to something else >>> set it to something else, therefore I think the comment about 'phy, >>> reset, clock' is irrelevant. >>> >>> You can very well add ie. >>> { .compatible = "allwinner,sun5i-a13-ohci", .data = TYPE_FOO }, >>> >>> And then do >>> >>> if (dev_get_driver_data(...) == TYPE_FOO) >>> priv->phy_index = bar; >>> else >>> priv->.......; >>> >>> If you think this is not possible, please do explain why in detail. >> >> Can I expect a new patchset using DT properly ? > > Yes Marek, I'm working on infact I'm trying to get these SOC's specs > out from musb and writing phy driver for that matter. Good!
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index d328df9..2c82d0a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -270,17 +270,18 @@ struct sunxi_ccm_reg { #define AXI_GATE_OFFSET_DRAM 0 /* ahb_gate0 offsets */ +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) +#define AHB_GATE_OFFSET_USB_OHCI3 31 +#define AHB_GATE_OFFSET_USB_OHCI2 30 +#define AHB_GATE_OFFSET_USB_OHCI1 29 +#define AHB_GATE_OFFSET_USB_OHCI0 28 +#define AHB_GATE_OFFSET_USB_EHCI3 27 +#define AHB_GATE_OFFSET_USB_EHCI2 26 +#define AHB_GATE_OFFSET_USB_EHCI1 25 +#define AHB_GATE_OFFSET_USB_EHCI0 24 +#else #define AHB_GATE_OFFSET_USB_OHCI1 30 #define AHB_GATE_OFFSET_USB_OHCI0 29 -#ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define AHB_GATE_OFFSET_USB_EHCI2 27 -#define AHB_GATE_OFFSET_USB_EHCI1 26 -#define AHB_GATE_OFFSET_USB_EHCI0 25 -#else #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif @@ -339,13 +340,10 @@ struct sunxi_ccm_reg { #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) #ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18) -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19) +#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) +#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) +#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) +#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) #else #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 6ecb7c4..f40228e 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -48,10 +48,17 @@ static int ehci_usb_probe(struct udevice *dev) #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; #endif +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ + priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST; +#else priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; +#endif priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; - priv->phy_index++; /* Non otg phys start at 1 */ +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) + priv->phy_index++; /* older chips do not have EHCI with OTG */ +#endif setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask); diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index 133774f..4b8a403 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -51,11 +51,18 @@ static int ohci_usb_probe(struct udevice *dev) extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; #endif priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; +#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) + /* Newer chips have a EHCI/OHCI host pair for OTG host mode */ + priv->phy_index = ((uintptr_t)regs - (SUNXI_USB0_BASE + 0x400)) / BASE_DIST; +#else priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; +#endif priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST; priv->usb_gate_mask <<= priv->phy_index; - priv->phy_index++; /* Non otg phys start at 1 */ +#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) + priv->phy_index++; /* older chips do not have OHCI with OTG */ +#endif setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask);