[U-Boot,v3,23/30] sunxi: clock: Fix clock gating for A64

Message ID	1517156391-11353-24-git-send-email-jagan@amarulasolutions.com
State	Changes Requested
Delegated to:	Marek Vasut
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Jagan Teki <jagannadh.teki@gmail.com> To: u-boot@lists.denx.de Date: Sun, 28 Jan 2018 21:49:44 +0530 Message-Id: <1517156391-11353-24-git-send-email-jagan@amarulasolutions.com> In-Reply-To: <1517156391-11353-1-git-send-email-jagan@amarulasolutions.com> References: <1517156391-11353-1-git-send-email-jagan@amarulasolutions.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Subject: [U-Boot] [PATCH v3 23/30] sunxi: clock: Fix clock gating for A64 Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	musb: sunxi: Add OTG-Peripheral support for Allwineer H3/H5/A64 \| expand [U-Boot,v3,00/30] musb: sunxi: Add OTG-Peripheral support for Allwineer H3/H5/A64 [U-Boot,v3,01/30] sunxi: h3: Sync OTG and HCI nodes from Linux DT [U-Boot,v3,02/30] sunxi: musb: Add fifo config for H3 [U-Boot,v3,03/30] sunxi: Fix USB PHY index for H3/H5/A64 [U-Boot,v3,04/30] sunxi: musb: Hack dynamic fifo support for H3 OTG [U-Boot,v3,05/30] sunxi: musb: Enable OTG device clock for H3 [U-Boot,v3,06/30] sunxi: usb_phy: setup USB PHY passby for USB0 on H3/H5/A64 [U-Boot,v3,07/30] sunxi: H3: set different otg base address per mode [U-Boot,v3,08/30] sunxi: usb_phy: Clear PHYCTL register before writing [U-Boot,v3,09/30] ARM: dts: sun8i-h3: bananapi-m2-plus: Sync usb otg nodes from Linux [U-Boot,v3,10/30] configs: bananapi-m2-plus: Enable USB OTG peripheral mode [U-Boot,v3,11/30] configs: sun50i: Drop CONFIG_USB_MAX_CONTROLLER_COUNT [U-Boot,v3,12/30] msub: sunxi: Update proper fifo config for H5 [U-Boot,v3,13/30] configs: sun50i: Set proper USB PHY count for H5 [U-Boot,v3,14/30] sunxi: usb_phy: Fix phy_config to handle all SOC's [U-Boot,v3,15/30] musb: sunxi: Add phy0 dual route support [U-Boot,v3,16/30] arm64: allwinner: h5: orangepi-pc2: Order nodes in alphabetic [U-Boot,v3,17/30] sunxi: arm64: Increase u-boot size on MMC environment [U-Boot,v3,18/30] sunxi: Add uENV partition on gpt partition table [U-Boot,v3,19/30] arm64: allwinner: h5: orangepi-pc2: Sync usb otg nodes from Linux [U-Boot,v3,20/30] configs: orangepi-pc2: Enable USB OTG peripheral mode [U-Boot,v3,21/30] arm64: allwinner: h5: orangepi-prime: Sync usb otg nodes from Linux [U-Boot,v3,22/30] configs: orangepi-prime: Enable USB OTG peripheral mode [U-Boot,v3,23/30] sunxi: clock: Fix clock gating for A64 [U-Boot,v3,24/30] configs: sun50i: Set proper USB PHY count for A64 [U-Boot,v3,25/30] musb: sunxi: Add support for A64 [U-Boot,v3,26/30] sunxi: usb_phy: Clear SIDDP for A64 [U-Boot,v3,27/30] arm64: allwinner: a64: bananapi-m64: Sync usb_otg node from Linux [U-Boot,v3,28/30] configs: bananapi-m64: Enable USB OTG peripheral mode [U-Boot,v3,29/30] arm64: allwinner: a64: olinuxino: Sync usb_otg from Linux [U-Boot,v3,30/30] configs: a64-olinuxino: Enable USB OTG peripheral mode

Message ID

1517156391-11353-24-git-send-email-jagan@amarulasolutions.com

State

Changes Requested

Delegated to:

Marek Vasut

Headers

From: Jagan Teki <jagannadh.teki@gmail.com>
To: u-boot@lists.denx.de
Date: Sun, 28 Jan 2018 21:49:44 +0530
Message-Id: <1517156391-11353-24-git-send-email-jagan@amarulasolutions.com>
In-Reply-To: <1517156391-11353-1-git-send-email-jagan@amarulasolutions.com>
References: <1517156391-11353-1-git-send-email-jagan@amarulasolutions.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Subject: [U-Boot] [PATCH v3 23/30] sunxi: clock: Fix clock gating for A64
Precedence: list
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

musb: sunxi: Add OTG-Peripheral support for Allwineer H3/H5/A64 | expand

Commit Message

Jagan Teki Jan. 28, 2018, 4:19 p.m. UTC

clock gating bits on a64 are different than H3_H5, so fix
them on clock_sun6i.h

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 624d624..30f75f7 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -270,7 +270,7 @@  struct sunxi_ccm_reg {
 #define AXI_GATE_OFFSET_DRAM		0
 
 /* ahb_gate0 offsets */
-#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#ifdef CONFIG_MACH_SUNXI_H3_H5
 #define AHB_GATE_OFFSET_USB_OHCI3	31
 #define AHB_GATE_OFFSET_USB_OHCI2	30
 #define AHB_GATE_OFFSET_USB_OHCI1	29
@@ -280,13 +280,19 @@  struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI1	25
 #define AHB_GATE_OFFSET_USB_EHCI0	24
 #define AHB_GATE_OFFSET_OTG_DEVICE	23
+#elif defined(CONFIG_MACH_SUN50I)
+#define AHB_GATE_OFFSET_USB_OHCI0	29
+#define AHB_GATE_OFFSET_USB_EHCI0	25
+#define AHB_GATE_OFFSET_OTG_DEVICE	23
 #else
 #define AHB_GATE_OFFSET_USB_OHCI1	30
 #define AHB_GATE_OFFSET_USB_OHCI0	29
 #define AHB_GATE_OFFSET_USB_EHCI1	27
 #define AHB_GATE_OFFSET_USB_EHCI0	26
 #endif
-#ifndef CONFIG_MACH_SUN8I_R40
+#ifdef CONFIG_MACH_SUN50I
+#define AHB_GATE_OFFSET_USB0		23
+#elif !defined(CONFIG_MACH_SUN8I_R40)
 #define AHB_GATE_OFFSET_USB0		24
 #else
 #define AHB_GATE_OFFSET_USB0		25

[U-Boot,v3,23/30] sunxi: clock: Fix clock gating for A64

Commit Message

Patch