From patchwork Tue Jan 9 15:44:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hannes Schmelzer X-Patchwork-Id: 857585 X-Patchwork-Delegate: agust@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zGGgw5CtJz9ryQ for ; Wed, 10 Jan 2018 02:45:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5089FC22090; Tue, 9 Jan 2018 15:45:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 14FC1C2205C; Tue, 9 Jan 2018 15:45:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 185CEC21F7C; Tue, 9 Jan 2018 15:45:01 +0000 (UTC) Received: from mail.schmelzer.or.at (mail.schmelzer.or.at [87.106.47.214]) by lists.denx.de (Postfix) with ESMTP id BF1B5C21C4F for ; Tue, 9 Jan 2018 15:45:00 +0000 (UTC) Received: from localhost (s15287728.onlinehome-server.info [127.0.0.1]) by hamspirit.at (Postfix) with ESMTP id A053F8F488B3; Tue, 9 Jan 2018 15:45:00 +0000 (UTC) Received: from mail.schmelzer.or.at ([127.0.0.1]) by localhost (s15287728.onlinehome-server.info [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ebXuw7l9Meaj; Tue, 9 Jan 2018 15:44:55 +0000 (UTC) Received: from scm-ws8.ad.schmelzer.or.at (188-22-125-132.adsl.highway.telekom.at [188.22.125.132]) by hamspirit.at (Postfix) with ESMTP id 216B88F488B5; Tue, 9 Jan 2018 15:44:55 +0000 (UTC) From: Hannes Schmelzer To: u-boot@lists.denx.de Date: Tue, 9 Jan 2018 16:44:42 +0100 Message-Id: <1515512687-16263-2-git-send-email-oe5hpm@oevsv.at> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515512687-16263-1-git-send-email-oe5hpm@oevsv.at> References: <1515512687-16263-1-git-send-email-oe5hpm@oevsv.at> Cc: trini@konsulko.com, Hannes Schmelzer Subject: [U-Boot] [PATCH v2 1/6] mach-omap2: add AM335x Display PLL register definition X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Adds the register definition of the Display DPLL Signed-off-by: Hannes Schmelzer --- Changes in v2: None arch/arm/include/asm/arch-am33xx/clock.h | 1 + arch/arm/mach-omap2/am33xx/clock_am33xx.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 5399bb8..9dbcd3a 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -104,6 +104,7 @@ extern const struct dpll_regs dpll_mpu_regs; extern const struct dpll_regs dpll_core_regs; extern const struct dpll_regs dpll_per_regs; extern const struct dpll_regs dpll_ddr_regs; +extern const struct dpll_regs dpll_disp_regs; extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS]; extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ]; extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ]; diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c index 1780bbd..9ab4d25 100644 --- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c +++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c @@ -52,6 +52,13 @@ const struct dpll_regs dpll_ddr_regs = { .cm_div_m2_dpll = CM_WKUP + 0xA0, }; +const struct dpll_regs dpll_disp_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, + .cm_div_m2_dpll = CM_WKUP + 0xA4, +}; + struct dpll_params dpll_mpu_opp100 = { CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1}; const struct dpll_params dpll_core_opp100 = {