From patchwork Thu Jan 4 07:07:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 855422 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JW5LWCZ0"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zBzS854kGz9s74 for ; Thu, 4 Jan 2018 18:09:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3D137C21DA9; Thu, 4 Jan 2018 07:08:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 24A70C21D5D; Thu, 4 Jan 2018 07:07:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 77D44C21DAB; Thu, 4 Jan 2018 07:07:47 +0000 (UTC) Received: from mail-pl0-f68.google.com (mail-pl0-f68.google.com [209.85.160.68]) by lists.denx.de (Postfix) with ESMTPS id AD456C21DBA for ; Thu, 4 Jan 2018 07:07:43 +0000 (UTC) Received: by mail-pl0-f68.google.com with SMTP id b12so588091plm.3 for ; Wed, 03 Jan 2018 23:07:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=QgeFBGs6FkD4cgqr/lxj+bUQWIHMXjQqKTwdPcsztdE=; b=JW5LWCZ0JZ9319wgkj6sWISKRsR59E89hu5TvOSwgGt2pcK1BNvHc8JLKK9A4UrOdT phDRW6injsNW4ccDupcAkNR6N+88Ilt/XaS1uMiRPpMKHY+B+L1A0Fq+9Dz6DObBKptW U9fBMKN9/C+MOcACRS1HMxRfi5x4M282a04pa7Y6Medu1RkXAbrkqQZHz5FY0HgXFf1p mMZ3zg/Grt6XRc5CGyH3MhurM1Yl2GnHCMrbT3jiIDWl4r3zvZGp5hKHI1N5qsipP/Z6 qY4f1pW0lotOixZUQymZ7NPnGUlv3lhr01CWL2bRsfLRey8/aR7PA7X/IbMPf6ybSJSU WF6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=QgeFBGs6FkD4cgqr/lxj+bUQWIHMXjQqKTwdPcsztdE=; b=nqRSS7vxY9BSg+9nuhNXuLH9y5vgWymdZcxi6SOU2UDcjxi0AyvBxYAMcjeVwM1iDa O7lm7hu+KsBMxCMhYxGlQGZRKfT4q0AkvyVbXGOuK3vfcy4FnW9WAkiCNGkzbD2e6A3U 6vjBrbhv7oK8xQXoT7+T1JUz9+LgOpZ/4th/NIYt2ub9HDdA2niIDgM0/gm48pEOOEAK wsHQW1NSFks7oJHjsCbEz13Fp7HIu6ECrcO7hq5pFOQJH49K0slokzgqLziyGqkFMecn dOy51BMtP05Oes01Z278nPfOVA32qUww8H16lvf2+1vW52eu76JwnjuJGF9DnaXK7SEP Bwmw== X-Gm-Message-State: AKGB3mIaAZHQ/6vYd/L98LFu/ajmSZRI6QaElxtCqkuL92pxXU5/sdbh caLA0PBkTQ+1BhHZMw7zzqV7gA== X-Google-Smtp-Source: ACJfBouezHtw8gRoKfYG8oxQnS7fwVn8sMstDVskMD58uz55L6YZ7aQzE9E420tBEnZ9ETY6t2L0Pg== X-Received: by 10.84.133.108 with SMTP id 99mr3832490plf.48.1515049662042; Wed, 03 Jan 2018 23:07:42 -0800 (PST) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id c8sm5716787pfm.92.2018.01.03.23.07.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 03 Jan 2018 23:07:41 -0800 (PST) From: Kever Yang To: u-boot@lists.denx.de Date: Thu, 4 Jan 2018 15:07:03 +0800 Message-Id: <1515049636-13513-5-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1515049636-13513-1-git-send-email-kever.yang@rock-chips.com> References: <1515049636-13513-1-git-send-email-kever.yang@rock-chips.com> Cc: Chris Packham Subject: [U-Boot] [PATCH v4 04/11] rockchip: rk322x: enable tpl support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them. Serial-changes: 2 - update upon latest source Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v4: - remove non-used MACRO define Changes in v3: - do not init ddr region in spl Changes in v2: None arch/arm/mach-rockchip/Kconfig | 9 +++ arch/arm/mach-rockchip/Makefile | 3 +- arch/arm/mach-rockchip/rk322x-board-spl.c | 63 +++++--------------- arch/arm/mach-rockchip/rk322x-board-tpl.c | 88 ++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds | 13 ++++ include/configs/rk322x_common.h | 9 ++- 6 files changed, 132 insertions(+), 53 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk322x-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 967290f..dbc197c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -46,9 +46,18 @@ config ROCKCHIP_RK322X bool "Support Rockchip RK3228/RK3229" select CPU_V7 select SUPPORT_SPL + select SUPPORT_TPL select SPL + select TPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL + select TPL_NEEDS_SEPARATE_STACK if TPL + select SPL_DRIVERS_MISC_SUPPORT + imply SPL_SERIAL_SUPPORT + imply TPL_SERIAL_SUPPORT select ROCKCHIP_BROM_HELPER select DEBUG_UART_BOARD_INIT + select TPL_LIBCOMMON_SUPPORT + select TPL_LIBGENERIC_SUPPORT help The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index e1b0519..3c14236 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -13,10 +13,11 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 35f4f97..89af1d9 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -5,77 +5,46 @@ */ #include -#include #include -#include #include -#include -#include -#include -#include -#include -#include -#include + +DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; } -DECLARE_GLOBAL_DATA_PTR; -#define GRF_BASE 0x11000000 -#define SGRF_BASE 0x10140000 - -#define DEBUG_UART_BASE 0x11030000 +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} void board_debug_uart_init(void) { -static struct rk322x_grf * const grf = (void *)GRF_BASE; - /* Enable early UART2 channel 1 on the RK322x */ - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK | GPIO1B2_MASK, - GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | - GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->con_iomux, - CON_IOMUX_UART2SEL_MASK, - CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); } -#define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { - struct udevice *dev; int ret; - /* - * Debug UART can be used from here if required: - * - * debug_uart_init(); - * printch('a'); - * printhex8(0x1234); - * printascii("string"); - */ - debug_uart_init(); - printascii("SPL Init"); - ret = spl_early_init(); if (ret) { - debug("spl_early_init() failed: %d\n", ret); + printf("spl_early_init() failed: %d\n", ret); hang(); } + preloader_console_init(); +} - rockchip_timer_init(); - printf("timer init done\n"); - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - printf("DRAM init failed: %d\n", ret); - return; - } +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); - /* Disable the ddr secure region setting to make it non-secure */ - rk_clrreg(SGRF_DDR_CON0, 0x4000); #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif + return 0; } +#endif diff --git a/arch/arm/mach-rockchip/rk322x-board-tpl.c b/arch/arm/mach-rockchip/rk322x-board-tpl.c new file mode 100644 index 0000000..a10a7a1 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x-board-tpl.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0x11000000 +#define SECURE_TIMER_BASE 0x110d0020 +#define SGRF_DDR_CON0 0x10150000 + +void board_debug_uart_init(void) +{ + static struct rk322x_grf * const grf = (void *)GRF_BASE; + /* Enable early UART2 channel 1 on the RK322x */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->con_iomux, + CON_IOMUX_UART2SEL_MASK, + CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); +} + +void secure_timer_init(void) +{ + writel(0, SECURE_TIMER_BASE + 0x10); + writel(0xffffffff, SECURE_TIMER_BASE); + writel(0xffffffff, SECURE_TIMER_BASE + 4); + writel(1, SECURE_TIMER_BASE + 0x10); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("TPL Init"); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + secure_timer_init(); + /* TODO: use arm generic timer instead for armv7 */ + rockchip_timer_init(); + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return; + } + + /* Disable the ddr secure region setting to make it non-secure */ + rk_clrreg(SGRF_DDR_CON0, 0x4000); +#if defined(CONFIG_TPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_TPL_BOARD_INIT) + back_to_bootrom(BROM_BOOT_NEXTSTAGE); +#endif +} diff --git a/arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds b/arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds new file mode 100644 index 0000000..841c803 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x/u-boot-tpl.lds @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2017 Rockchip Electronic Co.,Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE + +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE + +#include "../../cpu/u-boot-spl.lds" diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index b22169d..5536b58 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -20,11 +20,10 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_TEXT_BASE 0x60000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 -#define CONFIG_SPL_STACK 0x10088000 -#define CONFIG_SPL_TEXT_BASE 0x10081004 +#define CONFIG_SYS_TEXT_BASE 0x61000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x61100000 +#define CONFIG_SYS_LOAD_ADDR 0x61800800 +#define CONFIG_SPL_TEXT_BASE 0x60000000 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) #define CONFIG_ROCKCHIP_CHIP_TAG "RK32"