From patchwork Thu Dec 28 06:12:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 853330 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=amarulasolutions-com.20150623.gappssmtp.com header.i=@amarulasolutions-com.20150623.gappssmtp.com header.b="w4vu/wBW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3z6fg13Yfwz9ryr for ; Thu, 28 Dec 2017 17:18:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 297A7C21DDB; Thu, 28 Dec 2017 06:17:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 143F3C21DE8; Thu, 28 Dec 2017 06:15:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EFB8EC21DF0; Thu, 28 Dec 2017 06:14:36 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id AF942C21DDE for ; Thu, 28 Dec 2017 06:14:31 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id g2so20677530pli.8 for ; Wed, 27 Dec 2017 22:14:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3Mh/yHDKw8dzJ9lIQpS/k1cWzHmOWZ+jtJal9eLkGvw=; b=w4vu/wBWRkRwF6o+8o/JYbtTDdtNdiFqVFfa7zFKRhgP5ajhJiARL6oDQ5h0zq13hv qyQTQ8rD5fQrYIFXdHI6G/TtdZ/H5wqZvfdtauFMKItsrrGdCAgjPN23OM60Vi8+CC9a LDIvXpHKFTzivCF9+ZXOHTYVCin9OlHUAeW5wQ2VJqKOVmnkWJcykI+BpDYAXadMNAOB p2Xiw4si4f4TEQk7MJ6S5tSd7Ii1GWyAVO6sqYLIibafjKxpe0GgLpsvWPLpz+EOEp6d wwRuDpxpT5WhFUCrgedoiykGhpBGvK2xArREvzoXUYJTZhVc0bhsdvIhDeQymGMjWDzJ +ocA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3Mh/yHDKw8dzJ9lIQpS/k1cWzHmOWZ+jtJal9eLkGvw=; b=Z0UZVebMqqmAve7s7i0/7DUHEbDRPDrdv89RH7xIMi9ehhIBDEEySpe4vQotVeBG26 /Y1dIQq5FlczYdDvX7HwLl+KIWDiXH4yjyMdmHKSS2Padt5PMQJRREDUYkBd9WPpBDfY eOyyapLH8FDDWK0zrdoGTbmg//XzbjXd4u6fwV2msuLAX1zB4ZbiCaVNpTtfmW6hJ3N8 jContv2cKLWzmc8Z2ptZcl+y1TtaqdPX63AX53J/uv8nzmScheicJjrcD5DnBjlRev48 Y/2tCzHMV1jgs4scr53GwUfenU4qlHQ4A4ost0UJjWycaUuzLSzGGtJfDhick9C5VBEj UmHg== X-Gm-Message-State: AKGB3mIEOIyDsQ8gCsmlhcjnew5AHjsr5LHCb7C3rivtw5dQ+ZgcPYmw nEZBvd/r0AyfYf+RwKPe8ZrgLXcM X-Google-Smtp-Source: ACJfBovLIeJlnyvn3bSsx569Fptkql4Mz65gxWyNPSyynu+t+vvnyGuVjugUlnbZXXPwEs1mjMwerA== X-Received: by 10.159.202.142 with SMTP id p14mr30774579plo.444.1514441670103; Wed, 27 Dec 2017 22:14:30 -0800 (PST) Received: from localhost.localdomain ([27.59.176.39]) by smtp.gmail.com with ESMTPSA id s189sm16789697pgc.5.2017.12.27.22.14.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Dec 2017 22:14:29 -0800 (PST) From: Jagan Teki To: u-boot@lists.denx.de Date: Thu, 28 Dec 2017 11:42:26 +0530 Message-Id: <1514441553-27543-21-git-send-email-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514441553-27543-1-git-send-email-jagan@amarulasolutions.com> References: <1514441553-27543-1-git-send-email-jagan@amarulasolutions.com> Cc: Tom Rini Subject: [U-Boot] [PATCH v10 20/27] mtd: spi-nor: Add 4-byte addresswidth support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add 4-byte address supports, so-that SPI-NOR chips has > 16MiB should accessible. Signed-off-by: Jagan Teki --- drivers/mtd/spi-nor/m25p80.c | 1 + drivers/mtd/spi-nor/spi-nor.c | 38 ++++++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 6 +++++- 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/m25p80.c b/drivers/mtd/spi-nor/m25p80.c index 5465921..7af6f59 100644 --- a/drivers/mtd/spi-nor/m25p80.c +++ b/drivers/mtd/spi-nor/m25p80.c @@ -35,6 +35,7 @@ static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd) cmd[1] = addr >> (nor->addr_width * 8 - 8); cmd[2] = addr >> (nor->addr_width * 8 - 16); cmd[3] = addr >> (nor->addr_width * 8 - 24); + cmd[4] = addr >> (nor->addr_width * 8 - 32); } static int m25p_cmdsz(struct spi_nor *nor) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 8bf9e67..e0085cf 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -632,6 +632,38 @@ static int stm_unlock(struct udevice *dev, loff_t ofs, uint64_t len) } #endif +/* Enable/disable 4-byte addressing mode. */ +static int set_4byte(struct udevice *dev, const struct spi_nor_info *info, + int enable) +{ + struct spi_nor *nor = spi_nor_get_spi_nor_dev(dev); + const struct spi_nor_ops *ops = spi_nor_get_ops(dev); + int status; + bool need_wren = false; + u8 cmd; + + switch (JEDEC_MFR(info)) { + case SNOR_MFR_MICRON: + /* Some Micron need WREN command; all will accept it */ + need_wren = true; + case SNOR_MFR_MACRONIX: + case SNOR_MFR_WINBOND: + if (need_wren) + write_enable(dev); + + cmd = enable ? SNOR_OP_EN4B : SNOR_OP_EX4B; + status = ops->write_reg(dev, cmd, NULL, 0); + if (need_wren) + write_disable(dev); + + return status; + default: + /* Spansion style */ + nor->cmd_buf[0] = enable << 7; + return ops->write_reg(dev, SNOR_OP_BRWR, nor->cmd_buf, 1); + } +} + #ifdef CONFIG_SPI_NOR_MACRONIX static int macronix_quad_enable(struct udevice *dev) { @@ -873,6 +905,12 @@ int spi_nor_scan(struct spi_nor *nor) } nor->addr_width = 3; + if (mtd->size > SNOR_16MB_BOUN) { + nor->addr_width = 4; + ret = set_4byte(nor->dev, info, true); + if (ret) + goto err; + } /* Dummy cycles for read */ switch (nor->read_opcode) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e1688e2..fc4a649 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -63,6 +63,10 @@ #define SNOR_OP_BP 0x02 /* Byte program */ #define SNOR_OP_AAI_WP 0xad /* Auto addr increment word program */ +/* Used for Macronix and Winbond flashes. */ +#define SNOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ +#define SNOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ + /* Status Register bits. */ #define SR_WIP BIT(0) /* Write in progress */ #define SR_WEL BIT(1) /* Write enable latch */ @@ -84,7 +88,7 @@ /* Flash timeout values */ #define SNOR_READY_WAIT_PROG (2 * CONFIG_SYS_HZ) #define SNOR_READY_WAIT_ERASE (5 * CONFIG_SYS_HZ) -#define SNOR_MAX_CMD_SIZE 4 +#define SNOR_MAX_CMD_SIZE 6 #define SNOR_16MB_BOUN 0x1000000 /**