diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 94ad805..6816b5b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -932,6 +932,17 @@ config TARGET_LS1012ARDB
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
 
+config TARGET_LS1012A2G5RDB
+	bool "Support ls1012a2g5rdb"
+	select ARCH_LS1012A
+	select ARM64
+	select BOARD_LATE_INIT
+	help
+	  Support for Freescale LS1012A2G5RDB platform.
+	  The LS1012A 2G5 Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1012AFRDM
 	bool "Support ls1012afrdm"
 	select ARCH_LS1012A
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 51f48e1..3a0e129 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -90,7 +90,7 @@ config PSCI_RESET
 		   !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
 		   !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
 		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
-		   !TARGET_LS1012AQDS && \
+		   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
 		   !TARGET_LS2081ARDB && \
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cd540e9..0311d42 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -201,6 +201,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1046a-rdb.dtb \
 	fsl-ls1012a-qds.dtb \
 	fsl-ls1012a-rdb.dtb \
+	fsl-ls1012a-2g5rdb.dtb \
 	fsl-ls1012a-frdm.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
new file mode 100644
index 0000000..8c7f410
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts
@@ -0,0 +1,16 @@
+/*
+ * NXP ls1012a 2G5RDB board device tree source
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-rdb.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &duart0;
+	};
+};
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index 98231f9..d13b08e 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -15,3 +15,21 @@ config SYS_CONFIG_NAME
 source "board/freescale/common/Kconfig"
 
 endif
+
+if TARGET_LS1012A2G5RDB
+
+config SYS_BOARD
+        default "ls1012ardb"
+
+config SYS_VENDOR
+        default "freescale"
+
+config SYS_SOC
+        default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+        default "ls1012a2g5rdb"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
index 2cb38e7..a0a0d8d 100644
--- a/board/freescale/ls1012ardb/MAINTAINERS
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -8,3 +8,10 @@ F:	configs/ls1012ardb_qspi_defconfig
 M:	Sumit Garg <sumit.garg@nxp.com>
 S:	Maintained
 F:	configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+
+LS1012A2G5RDB BOARD
+M:      Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com>
+S:      Maintained
+F:      board/freescale/ls1012ardb/
+F:      include/configs/ls1012a2g5rdb.h
+F:      configs/ls1012a2g5rdb_qspi_defconfig
diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
index 453b432..c1d3415 100644
--- a/board/freescale/ls1012ardb/README
+++ b/board/freescale/ls1012ardb/README
@@ -52,3 +52,46 @@ U-boot 		| 1MB	| 0x4010_0000
 U-boot Env 	| 1MB	| 0x4020_0000
 PPA FIT image	| 2MB	| 0x4050_0000
 Linux ITB	| ~53MB | 0x40A0_0000
+
+LS1012A2G5RDB board Overview
+-----------------------
+ - SERDES Connections, 3 lanes supporting:
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+    - QSPI NOR flash memory
+ - USB 3.0
+    - one high-speed USB 2.0/3.0 port.
+ - SDIO WiFi, SPI
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - The LS1012A processor consists of two UART controllers,
+   out of which only UART1 is used on 2G5RDB.
+ - ARM JTAG support
+
+Major Difference b/w LS1012ARDB and LS1012A-2G5RDB
+--------------------------------------------------
+1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB
+2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs
+   of LS1012ARDB
+3. LS1012A-2G5RDB is not having Arduino header
+4. LS1012A-2G5RDB doesn't have PCI slot
+
+Booting Options
+---------------
+QSPI Flash
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4030_0000
+PPA FIT image	| 2MB	| 0x4040_0000
+PFE firmware	| 20K	| 0x00a0_0000
+Linux ITB	| ~53MB | 0x4100_0000
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index c0f6306..79b4ade 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -23,6 +23,7 @@
 #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
 
 
+#ifdef CONFIG_TARGET_LS1012ARDB
 void reset_phy(void)
 {
 	/* Through reset IO expander reset both RGMII and SGMII PHYs */
@@ -34,14 +35,22 @@ void reset_phy(void)
 	i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
 	mdelay(50);
 }
+#endif
 
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FSL_PFE
 	struct mii_dev *bus;
 	struct mdio_info mac1_mdio_info;
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 
+#ifdef CONFIG_TARGET_LS1012ARDB
 	reset_phy();
+#endif
+
+	int srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	init_pfe_scfg_dcfg_regs();
 
@@ -54,16 +63,35 @@ int board_eth_init(bd_t *bis)
 		return -1;
 	}
 
-	/* MAC1 */
-	ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
-	ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR,
-				     PHY_INTERFACE_MODE_SGMII);
-
-	/* MAC2 */
-	ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
-	ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR,
-				     PHY_INTERFACE_MODE_RGMII_TXID);
-
+	switch (srds_s1) {
+	case 0x3508:
+		/* MAC1 */
+		ls1012a_set_mdio(0, miiphy_get_dev_by_name(
+					DEFAULT_PFE_MDIO_NAME));
+		ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR,
+					     PHY_INTERFACE_MODE_SGMII);
+		/* MAC2 */
+		ls1012a_set_mdio(1, miiphy_get_dev_by_name(
+					DEFAULT_PFE_MDIO_NAME));
+		ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR,
+					     PHY_INTERFACE_MODE_RGMII_TXID);
+		break;
+	case 0x2208:
+		/* MAC1 */
+		ls1012a_set_mdio(0, miiphy_get_dev_by_name(
+					DEFAULT_PFE_MDIO_NAME));
+		ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR,
+					     PHY_INTERFACE_MODE_SGMII_2500);
+		/* MAC2 */
+		ls1012a_set_mdio(1, miiphy_get_dev_by_name(
+						DEFAULT_PFE_MDIO_NAME));
+		ls1012a_set_phy_address_mode(1, EMAC2_PHY_ADDR,
+					     PHY_INTERFACE_MODE_SGMII_2500);
+		break;
+	default:
+		printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
+		break;
+	}
 	cpu_eth_init(bis);
 #endif
 	return pci_eth_init(bis);
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 41283db..9675335 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -28,6 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
+#ifdef CONFIG_TARGET_LS1012ARDB
 	u8 in1;
 
 	puts("Board: LS1012ARDB ");
@@ -57,6 +58,9 @@ int checkboard(void)
 		puts(": bank2\n");
 	else
 		puts("unknown\n");
+#else
+	puts("Board: LS1012A2G5RDB ");
+#endif
 
 	return 0;
 }
@@ -148,10 +152,12 @@ int esdhc_status_fixup(void *blob, const char *compat)
 	 *	10 - eMMC Memory
 	 *	11 - SPI
 	 */
+#ifdef CONFIG_TARGET_LS1012ARDB
 	if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
 		printf("Error reading i2c boot information!\n");
 		return 0; /* Don't want to hang() on this error */
 	}
+#endif
 
 	mux_sdhc2 = (io & 0x0c) >> 2;
 	/* Enable SDHC2 only when use SDIO wifi and eMMC */
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
new file mode 100644
index 0000000..7556907
--- /dev/null
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -0,0 +1,46 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012A2G5RDB=y
+CONFIG_FSL_LS_PPA=y
+CONFIG_QSPI_AHB_INIT=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
new file mode 100644
index 0000000..6254b65
--- /dev/null
+++ b/include/configs/ls1012a2g5rdb.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012A2G5RDB_H__
+#define __LS1012A2G5RDB_H__
+
+#include "ls1012a_common.h"
+
+/* PFE Ethernet */
+#ifdef CONFIG_FSL_PFE
+#define EMAC1_PHY_ADDR          0x2
+#define EMAC2_PHY_ADDR          0x1
+#define CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_AQUANTIA
+#endif
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A2G5RDB_H__ */
