From patchwork Tue Nov 28 16:41:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 842229 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ymTxw4fLNz9t16 for ; Wed, 29 Nov 2017 03:43:32 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4063AC21E01; Tue, 28 Nov 2017 16:42:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EFC6EC21DF0; Tue, 28 Nov 2017 16:42:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 49555C21DC5; Tue, 28 Nov 2017 16:42:11 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id CB712C21DB1 for ; Tue, 28 Nov 2017 16:42:07 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vASGcomH005840; Tue, 28 Nov 2017 17:42:07 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2eexh9gr47-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 28 Nov 2017 17:42:07 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id EC0FD31; Tue, 28 Nov 2017 16:42:06 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D610D55F3; Tue, 28 Nov 2017 16:42:06 +0000 (GMT) Received: from localhost (10.75.127.49) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 28 Nov 2017 17:42:06 +0100 From: To: , Date: Tue, 28 Nov 2017 17:41:39 +0100 Message-ID: <1511887299-15776-3-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1511887299-15776-1-git-send-email-patrice.chotard@st.com> References: <1511887299-15776-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG1NODE2.st.com (10.75.127.2) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-28_10:, , signatures=0 Subject: [U-Boot] [PATCH 2/2] net: designware: add clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard This implementation manages several clocks, disable and free all of them in case of error during probe and in remove callback. Signed-off-by: Patrice Chotard Acked-by: Joe Hershberger --- drivers/net/designware.c | 43 +++++++++++++++++++++++++++++++++++++++++++ drivers/net/designware.h | 4 ++++ 2 files changed, 47 insertions(+) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 036d231..9207324 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -661,6 +662,35 @@ int designware_eth_probe(struct udevice *dev) u32 iobase = pdata->iobase; ulong ioaddr; int ret; +#ifdef CONFIG_CLK + int i, err, clock_nb; + + priv->clock_count = 0; + clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); + if (clock_nb > 0) { + priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), + GFP_KERNEL); + if (!priv->clocks) + return -ENOMEM; + + for (i = 0; i < clock_nb; i++) { + err = clk_get_by_index(dev, i, &priv->clocks[i]); + if (err < 0) + break; + + err = clk_enable(&priv->clocks[i]); + if (err) { + pr_err("failed to enable clock %d\n", i); + clk_free(&priv->clocks[i]); + goto clk_err; + } + priv->clock_count++; + } + } else if (clock_nb != -ENOENT) { + pr_err("failed to get clock phandle(%d)\n", clock_nb); + return clock_nb; + } +#endif #if defined(CONFIG_DM_REGULATOR) struct udevice *phy_supply; @@ -707,6 +737,15 @@ int designware_eth_probe(struct udevice *dev) debug("%s, ret=%d\n", __func__, ret); return ret; + +#ifdef CONFIG_CLK +clk_err: + ret = clk_release_all(priv->clocks, priv->clock_count); + if (ret) + pr_err("failed to disable all clocks\n"); + + return err; +#endif } static int designware_eth_remove(struct udevice *dev) @@ -717,7 +756,11 @@ static int designware_eth_remove(struct udevice *dev) mdio_unregister(priv->bus); mdio_free(priv->bus); +#ifdef CONFIG_CLK + return clk_release_all(priv->clocks, priv->clock_count); +#else return 0; +#endif } const struct eth_ops designware_eth_ops = { diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 7992d0e..252cd24 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -239,6 +239,10 @@ struct dw_eth_dev { #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif +#ifdef CONFIG_CLK + struct clk *clocks; /* clock list */ + int clock_count; /* number of clock in clock list */ +#endif struct phy_device *phydev; struct mii_dev *bus;