From patchwork Tue Nov 28 07:02:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 841995 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="A5w9HYhh"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ymF3p0vSlz9rxj for ; Tue, 28 Nov 2017 18:02:46 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C0CB6C21DBA; Tue, 28 Nov 2017 07:02:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 75946C21D56; Tue, 28 Nov 2017 07:02:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4D847C21D56; Tue, 28 Nov 2017 07:02:39 +0000 (UTC) Received: from mail-pl0-f65.google.com (mail-pl0-f65.google.com [209.85.160.65]) by lists.denx.de (Postfix) with ESMTPS id 72637C21C4C for ; Tue, 28 Nov 2017 07:02:38 +0000 (UTC) Received: by mail-pl0-f65.google.com with SMTP id s10so10122919plj.5 for ; Mon, 27 Nov 2017 23:02:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=YeZvj92UGjZoLYL8Zzp6fD9SfRSmikWMUswJpiA6qNU=; b=A5w9HYhhZN6GcSjb4qc8TiRbVX+19pd/GhQAAvnYNNbpRNqn69NhiVBbZj+696LWrE OMoq3BZ60SFO0jbYgkcGOcVZIuJSzfYY3wz75jvXQEM2ZIx4m7A8OFLJCeTeyDfm2Oo9 JuA6kSwgef6YbrFn5xQ9074JmciVSIaSsE6BC/0c8b7ThRwUORa0JZ/yxnf6IlrCLqgA tdNQFcBpmiZ9ynCWqzNHXSMffSlWMQ1eAWkwwvYeG6SIJraHBBNl4Qu/2Tqe3ZC46oeU 6PEFKJRShWidwbFQwdy2X99ORHK6qcwRiOq3bkMQxmp7PF8fqWF33iiymJq3FB3DFRhA wYLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=YeZvj92UGjZoLYL8Zzp6fD9SfRSmikWMUswJpiA6qNU=; b=FaYjMYnfuB6q0KU3mUUrj2C9wlDpdcCaSxsO90FOEnPxK7qWsfpXGSTM5LhFA49RAY f07+amNF5izRQkXD0u46LzHihqSPrORDrLDZYTvtQ1k4HkPiFsMxjtwf/u8F6tWIoLEK hdBzWpj8CPSlU9MEF8NhmmBsu0A9qy5Hu62Mqp80uJp3l1NEMjle7S3T9ZT9HX1FXqGh QzrLk25wXuHIqPVIfo8cwRLApo/H4gyxqCKLf02XlIi5VWfheSkwamf06D8NCjU6rXjc yA2cJYE0CjXk6maNfh2xlb8DZ/ngLQwI5rkd23yVXf0YwYnd1x4iau8ZFgvhd1IU5qaZ xvog== X-Gm-Message-State: AJaThX5sDVSUGrpT1M2m9P723m2TNIH0Pm5/3wv1/jtz/FNmXpjlCDHX uiLTJuX4o8/sHqVCG16XafPLFw== X-Google-Smtp-Source: AGs4zMYaJyRMtZ77mk1by1+vqhsadhdlRtATBF6GhvvfDZVQ2JkidmYgjmkILfljPH0rkMLljLam3g== X-Received: by 10.84.179.165 with SMTP id b34mr3945674plc.372.1511852556410; Mon, 27 Nov 2017 23:02:36 -0800 (PST) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id i11sm52473488pfk.25.2017.11.27.23.02.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 27 Nov 2017 23:02:35 -0800 (PST) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 28 Nov 2017 15:02:28 +0800 Message-Id: <1511852549-15752-1-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 Cc: Elaine Zhang Subject: [U-Boot] [PATCH v2 1/2] drivers/reset: support rockchip reset drivers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Elaine Zhang Create driver to support all Rockchip SoCs soft reset. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); } reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl); i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c"; Signed-off-by: Elaine Zhang Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - fix Kconfig more than 80 length - use MACRO for reset bits in one reg - use rkclr/set_reg for reg access - add rockchip_reset_bind() - use dev_read_addr_size() instead of fdtdec_ drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-rockchip.c | 133 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 drivers/reset/reset-rockchip.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index ce46e27..97a78d7 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -74,4 +74,13 @@ config AST2500_RESET resets that are supported by watchdog. The main limitation though is that some reset signals, like I2C or MISC reset multiple devices. +config RESET_ROCKCHIP + bool "Reset controller driver for Rockchip SoCs" + depends on DM_RESET && CLK + default y + help + Support for reset controller on rockchip SoC. The main limitation + though is that some reset signals, like I2C or MISC reset multiple + devices. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 252cefe..7d7e080 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c new file mode 100644 index 0000000..01047a2 --- /dev/null +++ b/drivers/reset/reset-rockchip.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +/* + * Each reg has 16 bits reset signal for devices + * Note: Not including rk2818 and older SoCs + */ +#define ROCKCHIP_RESET_NUM_IN_REG 16 + +struct rockchip_reset_priv { + void __iomem *base; + /* Rockchip reset reg locate at cru controller */ + u32 reset_reg_offset; + /* Rockchip reset reg number */ + u32 reset_reg_num; +}; + +static int rockchip_reset_request(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num); + + if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num) + return -EINVAL; + + return 0; +} + +static int rockchip_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int rockchip_reset_assert(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG; + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, + priv->base + (bank * 4)); + + rk_setreg(priv->base + (bank * 4), BIT(offset)); + + return 0; +} + +static int rockchip_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG; + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, + priv->base + (bank * 4)); + + rk_clrreg(priv->base + (bank * 4), BIT(offset)); + + return 0; +} + +struct reset_ops rockchip_reset_ops = { + .request = rockchip_reset_request, + .free = rockchip_reset_free, + .rst_assert = rockchip_reset_assert, + .rst_deassert = rockchip_reset_deassert, +}; + +static int rockchip_reset_probe(struct udevice *dev) +{ + struct rockchip_reset_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_read_addr_size(dev, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0)) + return -EINVAL; + + addr += priv->reset_reg_offset; + priv->base = ioremap(addr, size); + + debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__, + priv->base, priv->reset_reg_offset, priv->reset_reg_num); + + return 0; +} + +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number) +{ + struct udevice *rst_dev; + struct rockchip_reset_priv *priv; + int ret; + + ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset", + dev_ofnode(pdev), &rst_dev); + if (ret) { + debug("Warning: No rockchip reset driver: ret=%d\n", ret); + return ret; + } + priv = malloc(sizeof(struct rockchip_reset_priv)); + priv->reset_reg_offset = reg_offset; + priv->reset_reg_num = reg_number; + rst_dev->priv = priv; + + return 0; +} + +U_BOOT_DRIVER(rockchip_reset) = { + .name = "rockchip_reset", + .id = UCLASS_RESET, + .probe = rockchip_reset_probe, + .ops = &rockchip_reset_ops, + .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv), +};