From patchwork Wed Nov 15 12:14:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 838148 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ycNfd0SF3z9s7G for ; Wed, 15 Nov 2017 23:17:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B4291C21D88; Wed, 15 Nov 2017 12:16:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 495FBC21DB9; Wed, 15 Nov 2017 12:15:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4BCDEC21D90; Wed, 15 Nov 2017 12:15:35 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 2B92EC21C45 for ; Wed, 15 Nov 2017 12:15:35 +0000 (UTC) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vAFCEDhe031738; Wed, 15 Nov 2017 13:15:34 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2e87mtku51-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 15 Nov 2017 13:15:33 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4549438; Wed, 15 Nov 2017 12:15:33 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 28867277; Wed, 15 Nov 2017 12:15:33 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 15 Nov 2017 13:15:32 +0100 From: To: , , , , Date: Wed, 15 Nov 2017 13:14:47 +0100 Message-ID: <1510748093-16433-6-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510748093-16433-1-git-send-email-patrice.chotard@st.com> References: <1510748093-16433-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG1NODE3.st.com (10.75.127.3) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-15_06:, , signatures=0 Subject: [U-Boot] [PATCH 05/11] clk: stm32f7: add STM32F4 support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard STM32F4 and STM32F7 RCC clock IP are very similar. Same driver can be used to managed RCC clock for these 2 SoCs. Differences between STM32F4 and F7 will be managed using different compatible string : _ overdrive clock is only supported by STM32F7 _ different sys_pll_psc parameters can be used between STM32F4 and STM32F7. Signed-off-by: Patrice Chotard Reviewed-by: Vikas Manocha --- drivers/clk/clk_stm32f7.c | 109 ++++++++++++++++++++++++++++------------------ 1 file changed, 66 insertions(+), 43 deletions(-) diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index eb8a5bf..4c69740 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -81,37 +81,51 @@ struct pll_psc { #define APB_PSC_8 0x6 #define APB_PSC_16 0x7 +struct stm32_clk_info { + struct pll_psc sys_pll_psc; + bool has_overdrive; +}; + +struct stm32_clk_info stm32f4_clk_info = { + /* 180 MHz */ + .sys_pll_psc = { + .pll_m = 8, + .pll_n = 360, + .pll_p = 2, + .pll_q = 8, + .ahb_psc = AHB_PSC_1, + .apb1_psc = APB_PSC_4, + .apb2_psc = APB_PSC_2, + }, + .has_overdrive = false, +}; + +struct stm32_clk_info stm32f7_clk_info = { + /* 200 MHz */ + .sys_pll_psc = { + .pll_m = 25, + .pll_n = 400, + .pll_p = 2, + .pll_q = 8, + .ahb_psc = AHB_PSC_1, + .apb1_psc = APB_PSC_4, + .apb2_psc = APB_PSC_2, + }, + .has_overdrive = true, +}; + struct stm32_clk { struct stm32_rcc_regs *base; struct stm32_pwr_regs *pwr_regs; + struct stm32_clk_info *info; }; -#if !defined(CONFIG_STM32_HSE_HZ) -#error "CONFIG_STM32_HSE_HZ not defined!" -#else -#if (CONFIG_STM32_HSE_HZ == 25000000) -#if (CONFIG_SYS_CLK_FREQ == 200000000) -/* 200 MHz */ -struct pll_psc sys_pll_psc = { - .pll_m = 25, - .pll_n = 400, - .pll_p = 2, - .pll_q = 8, - .ahb_psc = AHB_PSC_1, - .apb1_psc = APB_PSC_4, - .apb2_psc = APB_PSC_2 -}; -#endif -#else -#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" -#endif -#endif - static int configure_clocks(struct udevice *dev) { struct stm32_clk *priv = dev_get_priv(dev); struct stm32_rcc_regs *regs = priv->base; struct stm32_pwr_regs *pwr = priv->pwr_regs; + struct pll_psc sys_pll_psc = priv->info->sys_pll_psc; /* Reset RCC configuration */ setbits_le32(®s->cr, RCC_CR_HSION); @@ -148,17 +162,23 @@ static int configure_clocks(struct udevice *dev) while (!(readl(®s->cr) & RCC_CR_PLLRDY)) ; - /* Enable high performance mode, System frequency up to 200 MHz */ setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); - setbits_le32(&pwr->cr1, PWR_CR1_ODEN); - /* Infinite wait! */ - while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY)) - ; - /* Enable the Over-drive switch */ - setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN); - /* Infinite wait! */ - while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY)) - ; + + if (priv->info->has_overdrive) { + /* + * Enable high performance mode + * System frequency up to 200 MHz + */ + setbits_le32(&pwr->cr1, PWR_CR1_ODEN); + /* Infinite wait! */ + while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY)) + ; + /* Enable the Over-drive switch */ + setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN); + /* Infinite wait! */ + while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY)) + ; + } stm32_flash_latency_cfg(5); clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); @@ -273,22 +293,25 @@ static int stm32_clk_probe(struct udevice *dev) struct stm32_clk *priv = dev_get_priv(dev); fdt_addr_t addr; - addr = devfdt_get_addr(dev); + addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; priv->base = (struct stm32_rcc_regs *)addr; - - err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, - &args); - if (err) { - debug("%s: can't find syscon device (%d)\n", __func__, - err); - return err; + priv->info = (struct stm32_clk_info *)dev_get_driver_data(dev); + + if (priv->info->has_overdrive) { + err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, + &args); + if (err) { + debug("%s: can't find syscon device (%d)\n", __func__, + err); + return err; + } + + priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node); } - priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node); - configure_clocks(dev); return 0; @@ -318,8 +341,8 @@ static struct clk_ops stm32_clk_ops = { }; static const struct udevice_id stm32_clk_ids[] = { - { .compatible = "st,stm32f42xx-rcc"}, - { .compatible = "st,stm32f746-rcc"}, + { .compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32f4_clk_info}, + { .compatible = "st,stm32f746-rcc", .data = (ulong)&stm32f7_clk_info}, {} };