From patchwork Tue Nov 7 10:37:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rajesh Bhagat X-Patchwork-Id: 835222 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yWQrX50rpz9s74 for ; Tue, 7 Nov 2017 21:38:36 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 55A22C21E3D; Tue, 7 Nov 2017 10:38:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C19AAC21E66; Tue, 7 Nov 2017 10:37:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 16FD9C21E0F; Tue, 7 Nov 2017 10:37:46 +0000 (UTC) Received: from NAM01-BY2-obe.outbound.protection.outlook.com (mail-by2nam01on0059.outbound.protection.outlook.com [104.47.34.59]) by lists.denx.de (Postfix) with ESMTPS id 22BD9C21D6A for ; Tue, 7 Nov 2017 10:37:45 +0000 (UTC) Received: from BN3PR03CA0079.namprd03.prod.outlook.com (10.167.1.167) by CO2PR03MB2359.namprd03.prod.outlook.com (10.166.93.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.197.13; Tue, 7 Nov 2017 10:37:42 +0000 Received: from BY2FFO11FD025.protection.gbl (2a01:111:f400:7c0c::140) by BN3PR03CA0079.outlook.office365.com (2a01:111:e400:7a4d::39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.197.13 via Frontend Transport; Tue, 7 Nov 2017 10:37:42 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD025.mail.protection.outlook.com (10.1.15.214) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.178.5 via Frontend Transport; Tue, 7 Nov 2017 10:37:41 +0000 Received: from ubuntu1604.ap.freescale.net (ubuntu1604.ap.freescale.net [10.232.133.7]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id vA7AbZIU020046; Tue, 7 Nov 2017 03:37:38 -0700 From: Rajesh Bhagat To: Date: Tue, 7 Nov 2017 16:07:59 +0530 Message-ID: <1510051085-29787-2-git-send-email-rajesh.bhagat@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510051085-29787-1-git-send-email-rajesh.bhagat@nxp.com> References: <1510051085-29787-1-git-send-email-rajesh.bhagat@nxp.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131545246621808849; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(336005)(376002)(346002)(39380400002)(39860400002)(2980300002)(1109001)(1110001)(339900001)(189002)(199003)(86362001)(189998001)(6666003)(54906003)(356003)(47776003)(81156014)(81166006)(68736007)(305945005)(2950100002)(5820100001)(316002)(2351001)(105606002)(53936002)(85426001)(8676002)(8936002)(8656006)(77096006)(106466001)(50466002)(5660300001)(104016004)(23676003)(4326008)(2870700001)(6916009)(97736004)(575784001)(2906002)(33646002)(50226002)(498600001)(36756003)(76176999)(50986999); DIR:OUT; SFP:1101; SCL:1; SRVR:CO2PR03MB2359; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD025; 1:+k3eDfrvB1ezaMYDgPY9+Jh9qTEI6bG3jOykGntO9d5HOVJVVjcyGm5GPAXAFAjDryfUCX3mj7xf6ZrznwRjsjPkG5O/yBeQ8wSTkudWxKfQnxX0Fxk2ReI+Ow7FSxXU X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ee908ce8-a44f-4d4c-add9-08d525cb932c X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(4534020)(4628075)(201703131517081)(2017052603199); SRVR:CO2PR03MB2359; X-Microsoft-Exchange-Diagnostics: 1; CO2PR03MB2359; 3:pVJjBWh+SX3GJZ2NIoXMWVWuhf2tFEpWYojrj3wwbD/sGqa5T9SAp83MMFDI+Mhk8xhfLxOMqTNPHAQOM5sq3kUHwFRmygz4PjacQLtdZNVu2cJR2bXq3h+ctTjBmYMGJsPpR7jbxuJc3JN+ZSJaTOJ1NwnbOmb8/qzZCryyvBCNGQjiZZF6hFArrHtVSpNG+o4P18POmRRMwt9w/NgyvG2KgHMTndrppexnGlmMYkoaNQcuSUDBWZzp86sBrOm/0OJLMvHDdzzOOjeEbWAAjW+YX+gqst37nouOTquG+yea4IzCabGJAqHgetujLdJitmPI1WYwE8TWDMsWrOPlYjS7hiY4QasIyTfjK+HFjeI=; 25:xoIobQKOVQTVq/yef5p6+jGUUnFg7OaPKNIE1yTbXMmnZ1xGAnkbzWkVgDk+Zmu4UtASjbwsxjYo1faRCpt2x2CjIidJ2mkreeThEMNgpKoMchmmWt+iNFMhwHnXCN03E1kQiMLOxRFvgSkyuBo9748JH/MAVeynBMUUNlbDWGVXXAQx3eCnLKX55EtLVKWQVv16x7kvf+kmfHBwySb2YrGqeFLjChauoCurrHJjvqoxIuwJvYsOVECb7++5iTdormqR+pjYRcAyv8HE3yjIgy8oYBLNLLsLzO9PZ3+g2TlzBzVrGYLsnhUs9iw6x9wGznE29mBkgCW793Tl0+xKOw== X-MS-TrafficTypeDiagnostic: CO2PR03MB2359: X-Microsoft-Exchange-Diagnostics: 1; CO2PR03MB2359; 31:Ih1FCVtddIOKg6EoD717YnYhg+h24Zg81XQVstjz2AZOHWFfuZa43b7p1VGDT9fvjE38REZm1qfolGpZItSxxsXNQHk85vFtKHrOLLG6NvZubFgj8tMblcXti/vnjyBVvvebQt2ZCcTxeo4AS6/IcLjD++z1hqZYtAyoIos0usZuCmb6J3xKSqSBetGi6Msd4hym22JhGpM5IwPzDVYaRUY0+eZCWwkpuQp6GEtKeHg=; 4:bJZj3AI8Ya1mhkF1zBYhCxs7vWrZLhHJTdwIX4ES1GhQqSXiGlzanrLadTubXFK/PLCsCQ0yycccgByMpbsPqRkGqoS1VTCkaPhwppP8CSzstuDhaiuaTMgzu3yOQXAqtsJjfoaIxBSX7szK70FSuBTBiNVwYpw01Qw6qnoUYqhGL87ugbmo1JJQFxAJM9aH3rxlsiafWze6s8iI7+wg2AkjrQgLVPkLTT0nNNvjhhJhMUlZkLKdb5qQGZHLEpfgGW2WTt5wWLMIHeBTMHi3yySFb1yF4omZ06/cmTQGGUqxPrc89TKuBw3uxQ8d8F8E X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(2401047)(5005006)(8121501046)(10201501046)(100000703101)(100105400095)(93006095)(93001095)(3002001)(3231021)(6055026)(6096035)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(20161123565025)(20161123559100)(20161123563025)(20161123556025)(20161123561025)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:CO2PR03MB2359; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:CO2PR03MB2359; X-Forefront-PRVS: 0484063412 X-Microsoft-Exchange-Diagnostics: =?utf-8?q?1=3BCO2PR03MB2359=3B23=3AYxhA?= =?utf-8?q?ZgSd3XN8BfE7hem+/nHb9DLx3kTVTleFACDsjT3pdzlEVJ0nbkLSrPxU?= =?utf-8?q?3Hi+a1oshpALAyx1FLizScXgXUzc6twmeRjeg4XDgHJHxwq4qhrGFQNx?= =?utf-8?q?+9Xy4x2X8a6geRAqVNg7ZIMdIl7PqNmbeBgbFQxHZzKs8Q54cFm2cIs1?= =?utf-8?q?wa9yzE9/9/5KsVtSYE2kMi5F56cDfqUIPWr4gezi8RivHW+MLS0hUFhv?= =?utf-8?q?OonP5wcSLzKcEuNvF1edRuE+fPCH3p3Aft/bHwoeKO29hZ0UD9+2C51q?= =?utf-8?q?AyVP1naqoTKGZnvonVTgWU4vsjEU+QPKWvm2sR3MmawgZO/XWdJwZQ/J?= =?utf-8?q?ululMCdHFvFTPb6a/LAlVgh/oBSXEojlRa/4H7Ll+n7sh73vvhFHQCr8?= =?utf-8?q?Ty2LLXjrn2HUfhbZCt/KST1lmkRFNsge+zP/P4QvKdxafIxzgTB4haeQ?= =?utf-8?q?6id+Rjq6QBqaaVakAE8xFz4ws0dM//jB6ezMjus1uzKbgFsu3qzSZ2lO?= =?utf-8?q?An6h00O51vPXPYd5rM31ETzETfRF5fTXcWxvSkSao/lScXppQfB5dTmr?= =?utf-8?q?OCNPtWv3kzDBVZM7y6t3Wd5mSyXHgkv9ahUUimal73cDpdOqtlSYdfzx?= =?utf-8?q?vnsdboQkyoV8JTY5ePOIvyQtpgAwZ7VVLThX+NhBcUkTSsIelI9UNqGy?= =?utf-8?q?0MYGY+zbQ2SLJ1hyiwEL/avSQGm78rbQUhCbuDKSwquBnoAluUHLv7ot?= =?utf-8?q?KBawIB1fBn70zJumw0mHqq2rdYrQwvrkU1R3T8MHlKAS31uglvKMY12S?= =?utf-8?q?ZgdIpDECqinI4py6DgMhnEfvUqbzOVUhU+8YDFbdO1MmNhYNzqw3tx7d?= =?utf-8?q?7SGqdmHwruSHN1SQhmoMNMg9Jc+Z/UmiGlbbJZj+Cj7idkK/nWcJ77HZ?= =?utf-8?q?WFplWd9dzd3fuDW5ngzCKxEOFqxPGOjpvnSNHwHUWj8XKkGq8Fwnv1Qb?= =?utf-8?q?m5uYXj1MZj/ewRY68mbHFFLl6junefhuyavbosctwnJM/HhluxvakjIf?= =?utf-8?q?x2/YtTjEJ31xu2doY8mf9/+K+zvyhkoGqWkotDG3T9TF/hC3YI8ylQEI?= =?utf-8?q?q+6oQz7jeU/4pmG4CEb7n7ts+55DZ+vKnOzgZglqxnOum9bRxs9kH04a?= =?utf-8?q?p6lJkz7U9l4nq89z7aXsVV7R7o18kik5/B/oONG6H8tOzQjCeZYzkCdc?= =?utf-8?q?aVKNpIZssPXwxIE=3D?= X-Microsoft-Exchange-Diagnostics: 1; CO2PR03MB2359; 6:XYQ3MOvjmadI+EHj5HkydAlHd6JkNl0CsE0iugnvXZXEqrit2MZVKAelTACThhxRnMwD6Hw6FrTD6Z1eYD88NQihzRBhnJKQ8m+QiNU5CmsShwON9yjqP9PeqO6VlbCzu+ADlkUwfPAzdNaW6l8ScvKPMDNhHvF267vP7lbTR/4oGZdulq0p/ey1/phbqlDLOltdVa1tqD6tdm4hSjKrzdP3kxGqYRVgsAAshIsLIgSUrdiT3oTDfqFHZCa6LDyDSKd+JweTRWUNxZaFGPwQkq0yijANxuJVLKg5bLskUAQYsdUwSw8cCKkhkas+Oce5dRVDa7bQ8hOyZ6w50gjiCe8bkQgyE+rw9l4AXy+Jn/4=; 5:+FbQwI7TmlfLhx/OUCTuR7H/jDteghUCFR6ZtxOauoy8YMjmrOExEvwuMj3dA6KsAMs3NFDen7foms6HsyZ1UBHDgo5X+C9Z+VWepeBQQKpvWJRyhVPbguK5raCIYVgemX1XRIDJ0m6WDNSd+I95jIPuURhf6mk1VZKvhIDpV7U=; 24:gurCyuJCojcwwVxtLVRYG5Cvf4sH32fCUZ9boCJb0kXLOoiv7+gGt74tUwGbXkXP0JwlVuWhivdS79AWv6NhZkZA8H46CZNKKWSOIDJYqQ8=; 7:fxpCjORSAgsgMYFntzLxNii/8H58OQdxxlzEOSGIMoGLMsJtNgHZzq1xpTDUyH5qdY1z0jeEnhJ8I8eX0b0a/kRtPZK/pjv+qAqk4YSkfvlHkLqxXQn9ZbW75eyAUfTXKIkrQjBDbzwGU7XexfAc4y124wUD0GC4qoqdl19/Fpy9K3248wjlOJlBgNskTd1IEkcCmTD+Yz07g5pMAVQVr+Cjn17njRgqpsAvVJoLvDDX172LGvcHS2Q4VL8l6X0R SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2017 10:37:41.8688 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee908ce8-a44f-4d4c-add9-08d525cb932c X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO2PR03MB2359 Cc: priyanka.jain@nxp.com Subject: [U-Boot] [PATCH v4 1/7] armv8: lsch3: Add serdes and DDR voltage setup X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Adds SERDES voltage and reset SERDES lanes API and makes enable/disable DDR controller support 0.9V API common. Signed-off-by: Ashish Kumar Signed-off-by: Rajesh Bhagat --- Changes in v4: - Added local macros instead of magical numbers - Created macros to remove duplicate code Changes in v3: Restructured LS1088A VID support to use common VID driver Cosmetic review comments fixed Added __iomem for accessing registers Changes in v2: Checkpatch errors fixed .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 263 +++++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 34 +-- .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 34 +++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + 5 files changed, 316 insertions(+), 18 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 179cac6..6fbfbed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -158,6 +158,269 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, serdes_prtcl_map[NONE] = 1; } +__weak int get_serdes_volt(void) +{ + return -1; +} + +__weak int set_serdes_volt(int svdd) +{ + return -1; +} + +#define LNAGCR0_RESET_MASK 0xFF9FFFFF +#define LNAGCR0_RT_RSTB 0x00600000 +#define RSTCTL_RESET_MASK_1 0xFFFFFFBF +#define RSTCTL_RESET_MASK_2 0xFFFFFF1F +#define RSTCTL_RESET_MASK_3 0xFFFFFFEF +#define RSTCTL_RSTREQ 0x80000000 +#define RSTCTL_RSTERR 0x20000000 +#define RSTCTL_SDEN 0x00000020 +#define RSTCTL_SDRST_B 0x00000040 +#define RSTCTL_PLLRST_B 0x00000080 +#define RSTCTL_RST_DONE 0x40000000 +#define TCALCR_RESET_MASK 0xF7FFFFFF +#define TCALCR_CALRST_B 0x08000000 + +#define CAT2(x, y) CAT2_(x, y) +#define CAT2_(x, y) x ## y + +#define CAT3(x, y, z) CAT3_(x, y, z) +#define CAT3_(x, y, z) x ## y ## z + +#define DO_ENABLED_LANES_RESET(x) do { \ + cfg_tmp = CAT2(cfg_rcwsrds, x) & \ + CAT3(FSL_CHASSIS3_SRDS, x, _PRTCL_MASK); \ + cfg_tmp >>= CAT3(FSL_CHASSIS3_SRDS, x, _PRTCL_SHIFT); \ + \ + for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { \ + reg = in_le32(&CAT3(serdes, x, _base)->lane[i].gcr0); \ + reg &= LNAGCR0_RESET_MASK; \ + out_le32(&CAT3(serdes, x, _base)->lane[i].gcr0, reg); \ + } \ +} while (0) + +#define DO_PLL_RESET(cfg_tmp, x) do { \ + for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { \ + reg = in_le32(&CAT3(serdes, x, _base)->bank[i].rstctl); \ + reg &= RSTCTL_RESET_MASK_1; \ + reg |= RSTCTL_RSTREQ; \ + out_le32(&CAT3(serdes, x, _base)->bank[i].rstctl, reg); \ + } \ + udelay(1); \ + \ + reg = in_le32(&CAT3(serdes, x, _base)->bank[i].rstctl); \ + reg &= RSTCTL_RESET_MASK_2; \ + out_le32(&CAT3(serdes, x, _base)->bank[i].rstctl, reg); \ +} while (0) + +#define DO_RX_TX_CAL_RESET(x) do { \ + reg = in_le32(&CAT3(serdes, x, _base)->srdstcalcr); \ + reg &= TCALCR_RESET_MASK; \ + out_le32(&CAT3(serdes, x, _base)->srdstcalcr, reg); \ + reg = in_le32(&CAT3(serdes, x, _base)->srdsrcalcr); \ + reg &= TCALCR_RESET_MASK; \ + out_le32(&CAT3(serdes, x, _base)->srdsrcalcr, reg); \ +} while (0) + +#define DO_RX_TX_CAL_RESET_COMP(x, i) do { \ + if (!(cfg_tmp == 0x3 && i == 1)) { \ + udelay(1); \ + reg = in_le32(&CAT3(serdes, x, _base)->srdstcalcr); \ + reg |= TCALCR_CALRST_B; \ + out_le32(&CAT3(serdes, x, _base)->srdstcalcr, reg); \ + reg = in_le32(&CAT3(serdes, x, _base)->srdsrcalcr); \ + reg |= TCALCR_CALRST_B; \ + out_le32(&CAT3(serdes, x, _base)->srdsrcalcr, reg); \ + } \ + udelay(1); \ +} while (0) + +#define DO_PLL_RESET_DONE(cfg_tmp, x) do { \ + for (i = 0; i < 2; i++) { \ + reg = in_le32(&CAT3(serdes, x, _base)->bank[i].pllcr0); \ + if (!(cfg_tmp & (0x1 << (1 - i))) && \ + ((reg >> 23) & 0x1)) { \ + reg = in_le32(&CAT3( \ + serdes, x, _base)->bank[i].rstctl); \ + reg |= RSTCTL_RST_DONE; \ + out_le32(&CAT3( \ + serdes, x, _base)->bank[i].rstctl, \ + reg); \ + } \ + } \ +} while (0) + +#define DO_SERDES_ENABLE(cfg_tmp, x) do { \ + for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { \ + reg = in_le32(&CAT3(serdes, x, _base)->bank[i].rstctl); \ + reg |= RSTCTL_SDEN; \ + out_le32(&CAT3(serdes, x, _base)->bank[i].rstctl, reg); \ + udelay(1); \ + \ + reg = in_le32(&CAT3(serdes, x, _base)->bank[i].rstctl); \ + reg |= RSTCTL_PLLRST_B; \ + out_le32(&CAT3(serdes, x, _base)->bank[i].rstctl, reg); \ + udelay(1); \ + /* Take the Rx/Tx calibration out of reset */ \ + DO_RX_TX_CAL_RESET_COMP(x, i); \ + } \ +} while (0) + +#define DO_PLL_LOCK(cfg_tmp, x) do { \ + for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) { \ + /* if the PLL is not locked, set RST_ERR */ \ + reg = in_le32(&CAT3(serdes, x, _base)->bank[i].pllcr0); \ + if (!((reg >> 23) & 0x1)) { \ + reg = in_le32(&CAT3( \ + serdes, x, _base)->bank[i].rstctl); \ + reg |= RSTCTL_RSTERR; \ + out_le32(&CAT3( \ + serdes, x, _base)->bank[i].rstctl, \ + reg); \ + } else { \ + udelay(1); \ + reg = in_le32(&CAT3( \ + serdes, x, _base)->bank[i].rstctl); \ + reg &= RSTCTL_RESET_MASK_3; \ + reg |= RSTCTL_SDRST_B; \ + out_le32(&CAT3( \ + serdes, x, _base)->bank[i].rstctl, \ + reg); \ + udelay(1); \ + } \ + } \ +} while (0) + +#define DO_ENABLED_LANES_RESET_COMP(x) do { \ + cfg_tmp = CAT2(cfg_rcwsrds, x) & \ + CAT3(FSL_CHASSIS3_SRDS, x, _PRTCL_MASK); \ + cfg_tmp >>= CAT3(FSL_CHASSIS3_SRDS, x, _PRTCL_SHIFT); \ + \ + for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { \ + reg = in_le32(&CAT3(serdes, x, _base)->lane[i].gcr0); \ + reg |= LNAGCR0_RT_RSTB; \ + out_le32(&CAT3(serdes, x, _base)->lane[i].gcr0, reg); \ + } \ +} while (0) + +int setup_serdes_volt(u32 svdd) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_serdes __iomem *serdes1_base; + u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); +#ifdef CONFIG_SYS_FSL_SRDS_2 + struct ccsr_serdes __iomem *serdes2_base; + u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); +#endif + u32 cfg_tmp, reg = 0; + int svdd_cur, svdd_tar; + int ret = 1; + int i; + + /* Only support switch SVDD to 900mV */ + if (svdd != 900) + return -1; + + /* Scale up to the LTC resolution is 1/4096V */ + svdd = (svdd * 4096) / 1000; + + svdd_tar = svdd; + svdd_cur = get_serdes_volt(); + if (svdd_cur < 0) + return -EINVAL; + + debug("%s: current SVDD: %x; target SVDD: %x\n", + __func__, svdd_cur, svdd_tar); + if (svdd_cur == svdd_tar) + return 0; + + serdes1_base = (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR; +#ifdef CONFIG_SYS_FSL_SRDS_2 + serdes2_base = (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); +#endif + + /* Put the all enabled lanes in reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + DO_ENABLED_LANES_RESET(1); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + DO_ENABLED_LANES_RESET(2); +#endif + + /* Put the all enabled PLL in reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcwsrds1 & 0x3; + DO_PLL_RESET(cfg_tmp, 1); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcwsrds1 & 0xC; + cfg_tmp >>= 2; + DO_PLL_RESET(cfg_tmp, 2); +#endif + + /* Put the Rx/Tx calibration into reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + DO_RX_TX_CAL_RESET(1); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + DO_RX_TX_CAL_RESET(2); +#endif + + ret = set_serdes_volt(svdd); + if (ret < 0) { + printf("could not change SVDD\n"); + ret = -1; + } + + /* For each PLL that’s not disabled via RCW enable the SERDES */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcwsrds1 & 0x3; + DO_SERDES_ENABLE(cfg_tmp, 1); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcwsrds1 & 0xC; + cfg_tmp >>= 2; + DO_SERDES_ENABLE(cfg_tmp, 2); +#endif + + /* Wait for at atleast 625us, ensure the PLLs being reset are locked */ + udelay(800); + +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcwsrds1 & 0x3; + DO_PLL_LOCK(cfg_tmp, 1); +#endif + +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcwsrds1 & 0xC; + cfg_tmp >>= 2; + DO_PLL_LOCK(cfg_tmp, 2); +#endif + /* Take the all enabled lanes out of reset */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + DO_ENABLED_LANES_RESET_COMP(1); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + DO_ENABLED_LANES_RESET_COMP(2); +#endif + + /* For each PLL being reset, and achieved PLL lock set RST_DONE */ +#ifdef CONFIG_SYS_FSL_SRDS_1 + cfg_tmp = cfg_rcwsrds1 & 0x3; + DO_PLL_RESET_DONE(cfg_tmp, 1); +#endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + cfg_tmp = cfg_rcwsrds1 & 0xC; + cfg_tmp >>= 2; + DO_PLL_RESET_DONE(cfg_tmp, 2); +#endif + return ret; +} + void fsl_serdes_init(void) { #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 497a4b5..47d89b2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -513,23 +513,6 @@ static int setup_core_volt(u32 vdd) return board_setup_core_volt(vdd); } -#ifdef CONFIG_SYS_FSL_DDR -static void ddr_enable_0v9_volt(bool en) -{ - struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; - u32 tmp; - - tmp = ddr_in32(&ddr->ddr_cdr1); - - if (en) - tmp |= DDR_CDR1_V0PT9_EN; - else - tmp &= ~DDR_CDR1_V0PT9_EN; - - ddr_out32(&ddr->ddr_cdr1, tmp); -} -#endif - int setup_chip_volt(void) { int vdd; @@ -598,6 +581,23 @@ void fsl_lsch2_early_init_f(void) } #endif +#ifdef CONFIG_SYS_FSL_DDR +void ddr_enable_0v9_volt(bool en) +{ + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + tmp = ddr_in32(&ddr->ddr_cdr1); + + if (en) + tmp |= DDR_CDR1_V0PT9_EN; + else + tmp &= ~DDR_CDR1_V0PT9_EN; + + ddr_out32(&ddr->ddr_cdr1, tmp); +} +#endif + #ifdef CONFIG_QSPI_AHB_INIT /* Enable 4bytes address support and fast read */ int qspi_ahb_init(void) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 12fd6b8..9becdf3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -164,6 +164,7 @@ void fsl_rgmii_init(void); #ifdef CONFIG_FSL_LSCH2 const char *serdes_clock_to_string(u32 clock); int get_serdes_protocol(void); +#endif #ifdef CONFIG_SYS_HAS_SERDES /* Get the volt of SVDD in unit mV */ int get_serdes_volt(void); @@ -172,6 +173,5 @@ int set_serdes_volt(int svdd); /* The target volt of SVDD in unit mV */ int setup_serdes_volt(u32 svdd); #endif -#endif #endif /* __FSL_SERDES_H__ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 957e23b..47e8b5a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -387,5 +387,39 @@ struct ccsr_reset { u32 ip_rev2; /* 0xbfc */ }; +struct ccsr_serdes { + struct { + u32 rstctl; /* Reset Control Register */ + u32 pllcr0; /* PLL Control Register 0 */ + u32 pllcr1; /* PLL Control Register 1 */ + u32 pllcr2; /* PLL Control Register 2 */ + u32 pllcr3; /* PLL Control Register 3 */ + u32 pllcr4; /* PLL Control Register 4 */ + u32 pllcr5; /* PLL Control Register 5 */ + u8 res[0x20 - 0x1c]; + } bank[2]; + u8 res1[0x90 - 0x40]; + u32 srdstcalcr; /* TX Calibration Control */ + u32 srdstcalcr1; /* TX Calibration Control1 */ + u8 res2[0xa0 - 0x98]; + u32 srdsrcalcr; /* RX Calibration Control */ + u32 srdsrcalcr1; /* RX Calibration Control1 */ + u8 res3[0xb0 - 0xa8]; + u32 srdsgr0; /* General Register 0 */ + u8 res4[0x800 - 0xb4]; + struct serdes_lane { + u32 gcr0; /* General Control Register 0 */ + u32 gcr1; /* General Control Register 1 */ + u32 gcr2; /* General Control Register 2 */ + u32 ssc0; /* Speed Switch Control 0 */ + u32 rec0; /* Receive Equalization Control 0 */ + u32 rec1; /* Receive Equalization Control 1 */ + u32 tec0; /* Transmit Equalization Control 0 */ + u32 ssc1; /* Speed Switch Control 1 */ + u8 res1[0x840 - 0x820]; + } lane[8]; + u8 res5[0x19fc - 0xa00]; +}; + #endif /*__ASSEMBLY__*/ #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 247f09e..8c242c0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -125,6 +125,7 @@ int setup_chip_volt(void); /* Setup core vdd in unit mV */ int board_setup_core_volt(u32 vdd); #endif +void ddr_enable_0v9_volt(bool en); void cpu_name(char *name); #ifdef CONFIG_SYS_FSL_ERRATUM_A009635