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[86.156.77.147]) by smtp.gmail.com with ESMTPSA id p49sm11303058wrc.61.2017.11.03.03.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Nov 2017 03:10:59 -0700 (PDT) From: Martyn Welch X-Google-Original-From: Martyn Welch Received: from martyn by hades with local (Exim 4.84_2) (envelope-from ) id 1eAYwD-0002bT-RM; Fri, 03 Nov 2017 10:10:57 +0000 To: u-boot@lists.denx.de Date: Fri, 3 Nov 2017 10:10:51 +0000 Message-Id: <1509703855-9948-5-git-send-email-martyn.welch@collabora.co.uk> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> References: <1509703855-9948-1-git-send-email-martyn.welch@collabora.co.uk> Cc: Nandor Han Subject: [U-Boot] [PATCH v4 4/8] arm: mx5: Add more register definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add register definitions require for video configuration. Signed-off-by: Nandor Han Signed-off-by: Martyn Welch Reviewed-by: Stefano Babic Cc: Stefano Babic --- arch/arm/include/asm/arch-mx5/crm_regs.h | 9 +++++++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index b61c7b9..c0af832 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -210,6 +210,15 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET 26 +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK (0x7 << 26) +#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v) (((v) & 0x7) << 26) +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r) (((r) >> 26) & 0x7) + +#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5 + + /* Define the bits in register CSCDR2 */ #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 2b0dc1e..bc1288e 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -416,6 +416,34 @@ struct iomuxc { }; #endif + +#define IOMUXC_GPR2_BITMAP_SPWG 0 +#define IOMUXC_GPR2_BITMAP_JEIDA 1 + +#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6 +#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<