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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id z3sm6895006qkc.17.2017.10.18.18.16.41 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 18:16:42 -0700 (PDT) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Wed, 18 Oct 2017 18:20:58 -0700 Message-Id: <1508376060-29425-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1508376060-29425-1-git-send-email-bmeng.cn@gmail.com> References: <1508376060-29425-1-git-send-email-bmeng.cn@gmail.com> Cc: Stefan Roese Subject: [U-Boot] [PATCH 7/9] x86: braswell: cherryhill: Update dts for SPI lock down X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Intel Braswell FSP requires SPI controller settings to be locked down, let's do this in the chrryhill.dts and remove previous Kconfig option. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/braswell/Kconfig | 4 ---- arch/x86/dts/cherryhill.dts | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig index 616f228..31ac279 100644 --- a/arch/x86/cpu/braswell/Kconfig +++ b/arch/x86/cpu/braswell/Kconfig @@ -31,8 +31,4 @@ config FSP_ADDR hex default 0xfff20000 -config FSP_LOCKDOWN_SPI - bool - default y - endif diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts index 840a669..41e72f3 100644 --- a/arch/x86/dts/cherryhill.dts +++ b/arch/x86/dts/cherryhill.dts @@ -143,6 +143,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "intel,ich9-spi"; + intel,spi-lock-down; spi-flash@0 { #address-cells = <1>;