From patchwork Mon Oct 9 09:41:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 823154 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3y9ZzC2Qxnz9tXv for ; Mon, 9 Oct 2017 20:42:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 01DEEC21DCA; Mon, 9 Oct 2017 09:42:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 27B7DC21DD7; Mon, 9 Oct 2017 09:41:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5562DC21C34; Mon, 9 Oct 2017 09:41:30 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 12D01C21C34 for ; Mon, 9 Oct 2017 09:41:30 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v999cd5w024338; Mon, 9 Oct 2017 11:41:29 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2dem24kuuq-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 09 Oct 2017 11:41:29 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3A8BD46; Mon, 9 Oct 2017 09:41:28 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id ED11C24AF; Mon, 9 Oct 2017 09:41:27 +0000 (GMT) Received: from localhost (10.75.127.49) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Mon, 9 Oct 2017 11:41:27 +0200 From: To: , , , Date: Mon, 9 Oct 2017 11:41:24 +0200 Message-ID: <1507542084-15068-3-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1507542084-15068-1-git-send-email-patrice.chotard@st.com> References: <1507542084-15068-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG8NODE3.st.com (10.75.127.24) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-09_02:, , signatures=0 Subject: [U-Boot] [PATCH 2/2] dm: clk: fix PWR_CR3 register's bit 2 name X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Fix bit 2 name of PWR_CR3 register to match with the last STM32H7 reference manual available here : http://www.st.com/content/st_com/en/support/resources/ resource-selector.html?querycriteria=productId=SS1951$$ resourceCategory=technical_literature$$resourceType=reference_manual Update also comment about voltage scaling 1 values Signed-off-by: Patrice Chotard Reviewed-by: Vikas Manocha --- drivers/clk/clk_stm32h7.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c index 9ca497a..ffa902d 100644 --- a/drivers/clk/clk_stm32h7.c +++ b/drivers/clk/clk_stm32h7.c @@ -109,7 +109,7 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPISRC_PER_CK 3 #define PWR_CR3 0x0c -#define PWR_CR3_SDEN BIT(2) +#define PWR_CR3_SCUEN BIT(2) #define PWR_D3CR 0x18 #define PWR_D3CR_VOS_MASK GENMASK(15, 14) #define PWR_D3CR_VOS_SHIFT 14 @@ -361,11 +361,11 @@ int configure_clocks(struct udevice *dev) writel(0x0, ®s->d2ccip1r); writel(0x0, ®s->d2ccip2r); - /* Set voltage scaling at scale 1 */ + /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */ clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK, VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT); - /* disable step down converter */ - clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SDEN); + /* Lock supply configuration update */ + clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN); while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY)) ;