From patchwork Wed Sep 27 13:44:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 819167 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3y2JzJ2pKXz9tXy for ; Wed, 27 Sep 2017 23:47:24 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 1E0F9C21D7B; Wed, 27 Sep 2017 13:45:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9FF67C21DA6; Wed, 27 Sep 2017 13:45:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 73F5DC21C46; Wed, 27 Sep 2017 13:45:06 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 2E7AFC21C45 for ; Wed, 27 Sep 2017 13:45:06 +0000 (UTC) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v8RDiHAD013817; Wed, 27 Sep 2017 15:45:05 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2d8cw703rb-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 27 Sep 2017 15:45:05 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 85ABB3F; Wed, 27 Sep 2017 13:45:04 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 599D828F4; Wed, 27 Sep 2017 13:45:04 +0000 (GMT) Received: from localhost (10.75.127.45) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Wed, 27 Sep 2017 15:45:03 +0200 From: To: , , , Date: Wed, 27 Sep 2017 15:44:53 +0200 Message-ID: <1506519893-16509-7-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506519893-16509-1-git-send-email-patrice.chotard@st.com> References: <1506519893-16509-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-27_03:, , signatures=0 Subject: [U-Boot] [PATCH v1 6/6] serial: stm32x7: remove useless CONFIG_CLK and OF_CONTROL flag X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard This driver is currently used by STM32F7 and STM32H7 SoCs. As CONFIG_CLK and OF_CONTROL flags are set by default for these 2 SoCs, this flag becomes useless in this driver, so remove it. Signed-off-by: Patrice Chotard --- drivers/serial/serial_stm32x7.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c index 44e8b42..a5d529c 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32x7.c @@ -83,7 +83,9 @@ static int stm32_serial_pending(struct udevice *dev, bool input) static int stm32_serial_probe(struct udevice *dev) { struct stm32x7_serial_platdata *plat = dev_get_platdata(dev); + struct clk clk; fdt_addr_t base = plat->base; + int ret; bool stm32f4; u8 uart_enable_bit; @@ -91,10 +93,6 @@ static int stm32_serial_probe(struct udevice *dev) stm32f4 = plat->uart_info->stm32f4; uart_enable_bit = plat->uart_info->uart_enable_bit; -#ifdef CONFIG_CLK - int ret; - struct clk clk; - ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) return ret; @@ -104,7 +102,6 @@ static int stm32_serial_probe(struct udevice *dev) dev_err(dev, "failed to enable clock\n"); return ret; } -#endif plat->clock_rate = clk_get_rate(&clk); if (plat->clock_rate < 0) { @@ -125,7 +122,6 @@ static int stm32_serial_probe(struct udevice *dev) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) static const struct udevice_id stm32_serial_id[] = { { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info}, { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info}, @@ -143,7 +139,6 @@ static int stm32_serial_ofdata_to_platdata(struct udevice *dev) return 0; } -#endif static const struct dm_serial_ops stm32_serial_ops = { .putc = stm32_serial_putc,