| Message ID | 1503202245.2411444.1344976407451.JavaMail.root@advansee.com |
|---|---|
| State | Accepted |
| Commit | 82e1b543b51fb514731992eeb2a6bdcdc279950e |
| Delegated to: | Stefano Babic |
| Headers | show |
On 14/08/2012 22:33, Benoît Thébaudeau wrote: > The clock dividers that were used do not match at all the reference manual. They > were either completely broken, or came from an early silicon revision > incompatible with the current one. > > Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> > Cc: Stefano Babic <sbabic@denx.de> > --- > .../arch/arm/cpu/arm1136/mx35/generic.c | 48 ++++++++------------ > .../arch/arm/include/asm/arch-mx35/crm_regs.h | 42 ++++++----------- > 2 files changed, 31 insertions(+), 59 deletions(-) > > diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c > index e369c86..4af052c 100644 > --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c > +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c > @@ -171,17 +171,14 @@ static u32 get_ipg_per_clk(void) > u32 pdr4 = readl(&ccm->pdr4); > u32 div; > if (pdr0 & MXC_CCM_PDR0_PER_SEL) { > - div = (CCM_GET_DIVIDER(pdr4, > - MXC_CCM_PDR4_PER0_PRDF_MASK, > - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * > - (CCM_GET_DIVIDER(pdr4, It seems also to me that the current code is wrong if MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in figure 5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the second multiplier comes. > + div = CCM_GET_DIVIDER(pdr4, > MXC_CCM_PDR4_PER0_PODF_MASK, > - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); > + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; The name remains quite confusing. In the manual is PER0_DIV, which is the meaning of PODF here ? Anyway, the masks you set are correct, I agree. > } else { > div = CCM_GET_DIVIDER(pdr0, > MXC_CCM_PDR0_PER_PODF_MASK, > MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; > - freq /= get_ahb_div(pdr0); > + div *= get_ahb_div(pdr0); This does not change the behavior. > } > return freq / div; > } > @@ -199,19 +196,16 @@ u32 imx_get_uartclk(void) > freq = decode_pll(readl(&ccm->ppctl), > CONFIG_MX35_HCLK_FREQ); > } > - freq /= ((CCM_GET_DIVIDER(pdr4, > - MXC_CCM_PDR4_UART_PRDF_MASK, > - MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * > - (CCM_GET_DIVIDER(pdr4, > + freq /= CCM_GET_DIVIDER(pdr4, > MXC_CCM_PDR4_UART_PODF_MASK, > - MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); > + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; This is also right. I am only asking myself why it works correctly now. > return freq; > } > > unsigned int mxc_get_main_clock(enum mxc_main_clock clk) > { > u32 nfc_pdf, hsp_podf; > - u32 pll, ret_val = 0, usb_prdf, usb_podf; > + u32 pll, ret_val = 0, usb_podf; > struct ccm_regs *ccm = > (struct ccm_regs *)IMX_CCM_BASE; > > @@ -255,8 +249,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) > ret_val = pll / (nfc_pdf + 1); > break; > case USB_CLK: > - usb_prdf = (reg4 >> 25) & 0x7; > - usb_podf = (reg4 >> 22) & 0x7; > + usb_podf = (reg4 >> 22) & 0x3F; Agree again. The code seems generated from another manual. Maybe the USB_DIV field was split into two fields. With this in mind, there is no apparent error in current code, but it cannot be derived from the manual. > break; > default: > printf("Unknown clock: %d\n", clk); > @@ -287,11 +280,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) > case UART2_BAUD: > case UART3_BAUD: > clk_sel = mpdr3 & (1 << 14); > - pre_pdf = (mpdr4 >> 13) & 0x7; > - pdf = (mpdr4 >> 10) & 0x7; > + pdf = (mpdr4 >> 10) & 0x3F; Right ! The main issue about this patch is that it does not fix one problem, but a lot of. Really it should be split into several patches. Anyway, I will make some tests on the mx35 boards I have - if I will not get problems, I will push it, hoping that someone else can make some further tests. Best regards, Stefano
Hi Stefano, On Saturday, September 1, 2012 11:15:35 AM, Stefano Babic wrote: > On 14/08/2012 22:33, Benoît Thébaudeau wrote: > > The clock dividers that were used do not match at all the reference > > manual. They > > were either completely broken, or came from an early silicon > > revision > > incompatible with the current one. > > > > Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> > > Cc: Stefano Babic <sbabic@denx.de> > > --- > > .../arch/arm/cpu/arm1136/mx35/generic.c | 48 > > ++++++++------------ > > .../arch/arm/include/asm/arch-mx35/crm_regs.h | 42 > > ++++++----------- > > 2 files changed, 31 insertions(+), 59 deletions(-) > > > > diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c > > u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c > > index e369c86..4af052c 100644 > > --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c > > +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c > > @@ -171,17 +171,14 @@ static u32 get_ipg_per_clk(void) > > u32 pdr4 = readl(&ccm->pdr4); > > u32 div; > > if (pdr0 & MXC_CCM_PDR0_PER_SEL) { > > - div = (CCM_GET_DIVIDER(pdr4, > > - MXC_CCM_PDR4_PER0_PRDF_MASK, > > - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * > > - (CCM_GET_DIVIDER(pdr4, > > It seems also to me that the current code is wrong if > MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in > figure > 5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the > second multiplier comes. It looks like the current code is based on a pre(PRDF)-/post(PODF)-divider scheme. Perhaps the first silicon revision was different and incompatible, or it was just a bug in the older revisions of the reference manual. The history of the reference manual says that this figure and some CCM register descriptions have been updated at some point. Anyway, Linux does like my patch. > > + div = CCM_GET_DIVIDER(pdr4, > > MXC_CCM_PDR4_PER0_PODF_MASK, > > - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); > > + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; > > The name remains quite confusing. In the manual is PER0_DIV, which is > the meaning of PODF here ? It the abbreviation FSL uses for post-dividers. If the pre-divider is merged with the post-divider to form a single divider, the naming from the RM makes more sense. Do you want a new version changing this naming? > Anyway, the masks you set are correct, I agree. > > > } else { > > div = CCM_GET_DIVIDER(pdr0, > > MXC_CCM_PDR0_PER_PODF_MASK, > > MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; > > - freq /= get_ahb_div(pdr0); > > + div *= get_ahb_div(pdr0); > > This does not change the behavior. It does: Dividing twice in a row affects rounding. > > } > > return freq / div; > > } > > @@ -199,19 +196,16 @@ u32 imx_get_uartclk(void) > > freq = decode_pll(readl(&ccm->ppctl), > > CONFIG_MX35_HCLK_FREQ); > > } > > - freq /= ((CCM_GET_DIVIDER(pdr4, > > - MXC_CCM_PDR4_UART_PRDF_MASK, > > - MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * > > - (CCM_GET_DIVIDER(pdr4, > > + freq /= CCM_GET_DIVIDER(pdr4, > > MXC_CCM_PDR4_UART_PODF_MASK, > > - MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); > > + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; > > This is also right. I am only asking myself why it works correctly > now. It currently works... or not depending on the divider settings selected by board inits. As long as the bits in the current PRDF bit-fields are kept cleared (luck...), it works. > > return freq; > > } > > > > unsigned int mxc_get_main_clock(enum mxc_main_clock clk) > > { > > u32 nfc_pdf, hsp_podf; > > - u32 pll, ret_val = 0, usb_prdf, usb_podf; > > + u32 pll, ret_val = 0, usb_podf; > > struct ccm_regs *ccm = > > (struct ccm_regs *)IMX_CCM_BASE; > > > > @@ -255,8 +249,7 @@ unsigned int mxc_get_main_clock(enum > > mxc_main_clock clk) > > ret_val = pll / (nfc_pdf + 1); > > break; > > case USB_CLK: > > - usb_prdf = (reg4 >> 25) & 0x7; > > - usb_podf = (reg4 >> 22) & 0x7; > > + usb_podf = (reg4 >> 22) & 0x3F; > > Agree again. The code seems generated from another manual. Maybe the > USB_DIV field was split into two fields. With this in mind, there is > no > apparent error in current code, but it cannot be derived from the > manual. The resulting frequency is different here too if some PRDF bits are set. > > break; > > default: > > printf("Unknown clock: %d\n", clk); > > @@ -287,11 +280,10 @@ unsigned int mxc_get_peri_clock(enum > > mxc_peri_clock clk) > > case UART2_BAUD: > > case UART3_BAUD: > > clk_sel = mpdr3 & (1 << 14); > > - pre_pdf = (mpdr4 >> 13) & 0x7; > > - pdf = (mpdr4 >> 10) & 0x7; > > + pdf = (mpdr4 >> 10) & 0x3F; > > Right ! > > > The main issue about this patch is that it does not fix one problem, > but > a lot of. Really it should be split into several patches. Indeed, but these problems have a common root cause: wrong RM in some way. > Anyway, I > will > make some tests on the mx35 boards I have - if I will not get > problems, > I will push it, hoping that someone else can make some further tests. OK. I have also tested it on a board that I have here. The best test would be to set some PRDF bits and to scope the resulting frequency (e.g. with PER0_DIV and I²C SCL). I'm not sure I have already performed this specific test. I'll do that when possible. There is also stuff like AUTO_CON and AUTO_MUX_DIV that are now marked as reserved in the RM. I've kept this code since it can not be harmful contrary to the wrong decoding of the divider fields. Best regards, Benoît
On 03/09/2012 17:31, Benoît Thébaudeau wrote: > Hi Stefano, > Hi Benoît, >> It seems also to me that the current code is wrong if >> MXC_CCM_PDR0_PER_SEL is set. Maybe it was never set. As I see in >> figure >> 5-4, the ipg_per_clk depends only on pdr[21:16]. No idea where the >> second multiplier comes. > > It looks like the current code is based on a pre(PRDF)-/post(PODF)-divider > scheme. I thought the same. > Perhaps the first silicon revision was different and incompatible, or it > was just a bug in the older revisions of the reference manual. The history of > the reference manual says that this figure and some CCM register descriptions > have been updated at some point. Anyway, Linux does like my patch. > >>> + div = CCM_GET_DIVIDER(pdr4, >>> MXC_CCM_PDR4_PER0_PODF_MASK, >>> - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); >>> + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; >> >> The name remains quite confusing. In the manual is PER0_DIV, which is >> the meaning of PODF here ? > > It the abbreviation FSL uses for post-dividers. If the pre-divider is merged > with the post-divider to form a single divider, the naming from the RM makes > more sense. Do you want a new version changing this naming? Yes, make this small change - then from my point of view I am ready to merge it. Regards, Stefano
On 03/09/2012 17:55, Stefano Babic wrote: > Yes, make this small change - then from my point of view I am ready to > merge it. Nevermind - this is really a detail. I prefer to fix soon the bugs. Thanks for having discovered and fixed. I merge the series now. Regards, Stefano
On 14/08/2012 22:33, Benoît Thébaudeau wrote: > The clock dividers that were used do not match at all the reference manual. They > were either completely broken, or came from an early silicon revision > incompatible with the current one. > > Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> > Cc: Stefano Babic <sbabic@denx.de> > --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index e369c86..4af052c 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -171,17 +171,14 @@ static u32 get_ipg_per_clk(void) u32 pdr4 = readl(&ccm->pdr4); u32 div; if (pdr0 & MXC_CCM_PDR0_PER_SEL) { - div = (CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_PER0_PRDF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + div = CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_PER0_PODF_MASK, - MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); + MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1; } else { div = CCM_GET_DIVIDER(pdr0, MXC_CCM_PDR0_PER_PODF_MASK, MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; - freq /= get_ahb_div(pdr0); + div *= get_ahb_div(pdr0); } return freq / div; } @@ -199,19 +196,16 @@ u32 imx_get_uartclk(void) freq = decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ); } - freq /= ((CCM_GET_DIVIDER(pdr4, - MXC_CCM_PDR4_UART_PRDF_MASK, - MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * - (CCM_GET_DIVIDER(pdr4, + freq /= CCM_GET_DIVIDER(pdr4, MXC_CCM_PDR4_UART_PODF_MASK, - MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); + MXC_CCM_PDR4_UART_PODF_OFFSET) + 1; return freq; } unsigned int mxc_get_main_clock(enum mxc_main_clock clk) { u32 nfc_pdf, hsp_podf; - u32 pll, ret_val = 0, usb_prdf, usb_podf; + u32 pll, ret_val = 0, usb_podf; struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; @@ -255,8 +249,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) ret_val = pll / (nfc_pdf + 1); break; case USB_CLK: - usb_prdf = (reg4 >> 25) & 0x7; - usb_podf = (reg4 >> 22) & 0x7; + usb_podf = (reg4 >> 22) & 0x3F; if (reg4 & 0x200) { pll = get_mcu_main_clk(); } else { @@ -264,7 +257,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk) CONFIG_MX35_HCLK_FREQ); } - ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); + ret_val = pll / (usb_podf + 1); break; default: printf("Unknown clock: %d\n", clk); @@ -287,11 +280,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) case UART2_BAUD: case UART3_BAUD: clk_sel = mpdr3 & (1 << 14); - pre_pdf = (mpdr4 >> 13) & 0x7; - pdf = (mpdr4 >> 10) & 0x7; + pdf = (mpdr4 >> 10) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case SSI1_BAUD: pre_pdf = (mpdr2 >> 24) & 0x7; @@ -311,11 +303,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) break; case CSI_BAUD: clk_sel = mpdr2 & (1 << 7); - pre_pdf = (mpdr2 >> 16) & 0x7; - pdf = (mpdr2 >> 19) & 0x7; + pdf = (mpdr2 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case MSHC_CLK: pre_pdf = readl(&ccm->pdr1); @@ -328,27 +319,24 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk) break; case ESDHC1_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = mpdr3 & 0x7; - pdf = (mpdr3>>3) & 0x7; + pdf = mpdr3 & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case ESDHC2_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 8) & 0x7; - pdf = (mpdr3 >> 11) & 0x7; + pdf = (mpdr3 >> 8) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case ESDHC3_CLK: clk_sel = mpdr3 & 0x40; - pre_pdf = (mpdr3 >> 16) & 0x7; - pdf = (mpdr3 >> 19) & 0x7; + pdf = (mpdr3 >> 16) & 0x3F; ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / - ((pre_pdf + 1) * (pdf + 1)); + (pdf + 1); break; case SPDIF_CLK: clk_sel = mpdr3 & 0x400000; diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/crm_regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/crm_regs.h index 66bc1ba..f6b381b 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/crm_regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -32,8 +32,8 @@ #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) #define MXC_CCM_CCMR_ROMW_OFFSET 18 #define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) -#define MXC_CCM_CCMR_RAMW_OFFSET 21 -#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) +#define MXC_CCM_CCMR_RAMW_OFFSET 16 +#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16) #define MXC_CCM_CCMR_LPM_OFFSET 14 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) #define MXC_CCM_CCMR_UPE (1 << 9) @@ -47,7 +47,7 @@ #define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) #define MXC_CCM_PDR0_CKIL_SEL (1 << 15) #define MXC_CCM_PDR0_PER_PODF_OFFSET 12 -#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) +#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12) #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) #define MXC_CCM_PDR0_AUTO_CON 0x1 @@ -62,10 +62,8 @@ #define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 #define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) -#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 -#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 -#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) +#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 #define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR2_CSI_M_U (1 << 7) @@ -78,35 +76,23 @@ #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 #define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) #define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) -#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 -#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 -#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR3_UART_M_U (1 << 15) -#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 -#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) +#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16) +#define MXC_CCM_PDR3_UART_M_U (1 << 14) #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 -#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) +#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8) #define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) -#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 -#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 -#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) +#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F) #define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 #define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) -#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 -#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) #define MXC_CCM_PDR4_USB_PODF_OFFSET 22 -#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) -#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 -#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) +#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22) #define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 -#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) -#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 -#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) +#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16) #define MXC_CCM_PDR4_UART_PODF_OFFSET 10 -#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) +#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10) #define MXC_CCM_PDR4_USB_M_U (1 << 9) /* Bit definitions for RCSR */ @@ -257,10 +243,8 @@ #define MXC_CCM_COSR_CLKOSEL_OFFSET 0 #define MXC_CCM_COSR_CLKOEN (1 << 5) #define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) -#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) -#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 -#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) -#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 +#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10) +#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
The clock dividers that were used do not match at all the reference manual. They were either completely broken, or came from an early silicon revision incompatible with the current one. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> --- .../arch/arm/cpu/arm1136/mx35/generic.c | 48 ++++++++------------ .../arch/arm/include/asm/arch-mx35/crm_regs.h | 42 ++++++----------- 2 files changed, 31 insertions(+), 59 deletions(-)