From patchwork Wed Aug 16 17:32:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 802161 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xXc9S3Wkwz9t2y for ; Thu, 17 Aug 2017 03:42:04 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 32E86C21EAE; Wed, 16 Aug 2017 17:34:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5C47AC21EE6; Wed, 16 Aug 2017 17:33:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E166EC21EDC; Wed, 16 Aug 2017 17:33:05 +0000 (UTC) Received: from mail.theobroma-systems.com (vegas.theobroma-systems.com [144.76.126.164]) by lists.denx.de (Postfix) with ESMTPS id DBCA5C21E96 for ; Wed, 16 Aug 2017 17:33:00 +0000 (UTC) Received: from [86.59.122.178] (port=33209 helo=android.lan) by mail.theobroma-systems.com with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA256:128) (Exim 4.80) (envelope-from ) id 1di2Bf-0007dI-1B; Wed, 16 Aug 2017 19:32:59 +0200 From: Philipp Tomsich To: u-boot@lists.denx.de Date: Wed, 16 Aug 2017 19:32:22 +0200 Message-Id: <1502904758-7562-8-git-send-email-philipp.tomsich@theobroma-systems.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1502904758-7562-1-git-send-email-philipp.tomsich@theobroma-systems.com> References: <1502904758-7562-1-git-send-email-philipp.tomsich@theobroma-systems.com> Cc: Klaus Goger Subject: [U-Boot] [PATCH 07/18] rockchip: timer: implement timer_get_boot_us X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To make the Rockchip DM timer driver useful for the timing of bootstages, we need a few enhancements: - This implements timer_get_boot_us. - This avoids reinitialising the timer, if it has already been set up (e.g. by our TPL and SPL stages). Now, we have a single timebase ticking from TPL through the full U-Boot. - This adds support for reading the timer even before the device-model is ready: we find the timer via /chosen/tick-timer, then read its address and clock-frequency, and finally read the timeval directly). Signed-off-by: Philipp Tomsich Acked-by: Philipp Tomsich Reviewed-by: Simon Glass --- drivers/timer/rockchip_timer.c | 72 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 67 insertions(+), 5 deletions(-) diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index 831b7da..74bb002 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -25,17 +26,72 @@ struct rockchip_timer_priv { struct rk_timer *timer; }; -static int rockchip_timer_get_count(struct udevice *dev, u64 *count) +static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer) { - struct rockchip_timer_priv *priv = dev_get_priv(dev); uint64_t timebase_h, timebase_l; uint64_t cntr; - timebase_l = readl(&priv->timer->timer_curr_value0); - timebase_h = readl(&priv->timer->timer_curr_value1); + timebase_l = readl(&timer->timer_curr_value0); + timebase_h = readl(&timer->timer_curr_value1); - /* timers are down-counting */ cntr = timebase_h << 32 | timebase_l; + return cntr; +} + +#if CONFIG_IS_ENABLED(BOOTSTAGE) +ulong timer_get_boot_us(void) +{ + uint64_t ticks = 0; + uint32_t rate; + uint64_t us; + int ret; + + ret = dm_timer_init(); + + if (!ret) { + /* The timer is available */ + rate = timer_get_rate(gd->timer); + timer_get_count(gd->timer, &ticks); +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + } else if (ret == -EAGAIN) { + /* We have been called so early that the DM is not ready,... */ + ofnode node = offset_to_ofnode(-1); + struct rk_timer *timer = NULL; + + /* + * ... so we try to access the raw timer, if it is specified + * via the tick-timer property in /chosen. + */ + node = ofnode_get_chosen_node("tick-timer"); + if (!ofnode_valid(node)) { + debug("%s: no /chosen/tick-timer\n", __func__); + return 0; + } + + timer = (struct rk_timer *)ofnode_get_addr(node); + + /* This timer is down-counting */ + ticks = ~0uLL - rockchip_timer_get_curr_value(timer); + if (ofnode_read_u32(node, "clock-frequency", &rate)) { + debug("%s: could not read clock-frequency\n", __func__); + return 0; + } +#endif + } else { + return 0; + } + + us = (ticks * 1000) / rate; + return us; +} +#endif + +static int rockchip_timer_get_count(struct udevice *dev, u64 *count) +{ + struct rockchip_timer_priv *priv = dev_get_priv(dev); + uint64_t cntr = rockchip_timer_get_curr_value(priv->timer); + + /* timers are down-counting */ *count = ~0ull - cntr; return 0; } @@ -58,6 +114,12 @@ static int rockchip_timer_start(struct udevice *dev) const uint32_t reload_val_l = reload_val & 0xffffffff; const uint32_t reload_val_h = reload_val >> 32; + /* don't reinit, if the timer is already running and set up */ + if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 && + (readl(&priv->timer->timer_load_count0) == reload_val_l) && + (readl(&priv->timer->timer_load_count1) == reload_val_h)) + return 0; + /* disable timer and reset all control */ writel(0, &priv->timer->timer_ctrl_reg); /* write reload value */