From patchwork Fri Jul 28 19:22:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 795068 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xK0Fd4n8Rz9s65 for ; Sat, 29 Jul 2017 06:05:25 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6B28FC2219E; Fri, 28 Jul 2017 19:55:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9A26CC22107; Fri, 28 Jul 2017 19:40:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 70C81C222F0; Fri, 28 Jul 2017 19:29:48 +0000 (UTC) Received: from mail.theobroma-systems.com (vegas.theobroma-systems.com [144.76.126.164]) by lists.denx.de (Postfix) with ESMTPS id D25C5C2207D for ; Fri, 28 Jul 2017 19:29:38 +0000 (UTC) Received: from [86.59.122.178] (port=51261 helo=android.lan) by mail.theobroma-systems.com with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA256:128) (Exim 4.80) (envelope-from ) id 1dbArf-0003yU-8q; Fri, 28 Jul 2017 21:23:59 +0200 From: Philipp Tomsich To: u-boot@lists.denx.de Date: Fri, 28 Jul 2017 21:22:17 +0200 Message-Id: <1501269764-13969-46-git-send-email-philipp.tomsich@theobroma-systems.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1501269764-13969-1-git-send-email-philipp.tomsich@theobroma-systems.com> References: <1501269764-13969-1-git-send-email-philipp.tomsich@theobroma-systems.com> Cc: Albert Aribaud , Klaus Goger , Andy Yan Subject: [U-Boot] [PATCH v3 45/66] rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To enable the GMAC on the RK3368, we need to set up the clocking appropriately to generate a tx_clk for the MAC. This adds an implementation that implements the use of the <&ext_gmac> clock (i.e. an external 125MHz clock for RGMII provided by the PHY). This is the clock setup used by the boards currently supported by U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7). This includes the change from commit - rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- Changes in v3: None Changes in v2: None arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 3 +++ drivers/clk/rockchip/clk_rk3368.c | 19 +++++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 21f11e0..2b1197f 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -89,6 +89,9 @@ enum { MCU_CLK_DIV_SHIFT = 0, MCU_CLK_DIV_MASK = GENMASK(4, 0), + /* CLKSEL43_CON */ + GMAC_MUX_SEL_EXTCLK = BIT(8), + /* CLKSEL51_CON */ MMC_PLL_SEL_SHIFT = 8, MMC_PLL_SEL_MASK = GENMASK(9, 8), diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 1bed4e2..2b6c8da 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -338,6 +338,19 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate) } #endif +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, + ulong clk_id, ulong set_rate) +{ + /* + * This models the 'assigned-clock-parents = <&ext_gmac>' from + * the DTS and switches to the 'ext_gmac' clock parent. + */ + rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK); + return set_rate; +} +#endif + static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) { struct rk3368_clk_priv *priv = dev_get_priv(clk->dev); @@ -356,10 +369,12 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) ret = rk3368_mmc_set_clk(clk, rate); break; #endif +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) case SCLK_MAC: - /* nothing to do, as this is an external clock */ - ret = rate; + /* select the external clock */ + ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate); break; +#endif default: return -ENOENT; }