From patchwork Thu Jul 27 04:54:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 794212 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="c716Q7iq"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xJ05Z3Hqkz9s3T for ; Thu, 27 Jul 2017 14:54:58 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 239D1C22286; Thu, 27 Jul 2017 04:54:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A2898C222BA; Thu, 27 Jul 2017 04:54:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 18BE6C222A4; Thu, 27 Jul 2017 04:54:21 +0000 (UTC) Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by lists.denx.de (Postfix) with ESMTPS id EA32CC22259 for ; Thu, 27 Jul 2017 04:54:17 +0000 (UTC) Received: by mail-pg0-f65.google.com with SMTP id d193so19308921pgc.2 for ; Wed, 26 Jul 2017 21:54:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=YrmX/KIasU+foxNkhM20caIhB9MWazIRc0UVxacL5A4=; b=c716Q7iqJ+DBMkVBuxufUT0F3HnUgOykMfKQXCaX9BpJo+UC3bZYde1JMK9MIhhfus kkaG0aNJVjqWw2bBBGXrAaEC1nBkuJHu4f9SlA3bmVxSHWQPukL2ZkmEOactBg1eLwGb uXQR0bF0aafdUQNtBqjIm+DoqMyZ01k+eh1u++0r2akPVfe4mBxlzt4Y5/4G7gBWoF1v BAqWP5s+A1jwOIdt3I3yX/TaT/DkMGE03qzcwM0+EYPrHkUGVBAwQfYJrS2ot4jzJVaZ a9sIBNICYdhdh1m1c0lwiu7XQ/EX51ol0B6zzTN/IFHWCMBFNp0PT8ZOzwohNcw9lB31 ZETg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=YrmX/KIasU+foxNkhM20caIhB9MWazIRc0UVxacL5A4=; b=nhBf4wGstd0QMrQZxypOae6F3tZCRZgR3PW+satDbydjivcLOG6pb7gIO9+LSlrdTh DEkHScTSCcCsl5qSmpSKRaDjm5S6qMi7D6uDChcI2FjdyWweLr2EQD5ATU+nU4P7Ujfk paZ5OZEB7vT+8PJ9wz3Nwfa2fwukDTi0MvdORVwlMB3bowfitkco9FEn5k8Xxvhqjwko dncynsMZe4liGimRGZ/RYVYXP7RQMKhzuDBBy59TLLh4ht06hGsIJ1hiFWNuroNMgzsn CLlKycjzDaZGJSdaP+T5GtIoPqhBTVjydc1SAjaHSW98vjYRmtLxIqkdbmveQc09iJDP 7ZaQ== X-Gm-Message-State: AIVw1135g+7sYJdIqJmx0QnuPBqbeJ8Kdrys1olTpstNfPGPikPKWp+I P8ZYVY5KUBBgUA== X-Received: by 10.99.161.2 with SMTP id b2mr3031444pgf.243.1501131256605; Wed, 26 Jul 2017 21:54:16 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id v87sm210037pfi.48.2017.07.26.21.54.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Jul 2017 21:54:15 -0700 (PDT) From: Kever Yang To: sjg@chromium.org Date: Thu, 27 Jul 2017 12:54:01 +0800 Message-Id: <1501131242-14951-3-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1501131242-14951-1-git-send-email-kever.yang@rock-chips.com> References: <1501131242-14951-1-git-send-email-kever.yang@rock-chips.com> Cc: vagrant@debian.org, Jacob Chen , u-boot@lists.denx.de, William Zhang Subject: [U-Boot] [RESENT PATCH v2 3/4] rockchip: clk: update dwmmc clock div X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" dwmmc controller has default internal divider by 2, and we always provide double of the clock rate request by dwmmc controller. Sync code for all Rockchip SoC with: 4055b46 rockchip: clk: rk3288: fix mmc clock setting Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Acked-by: Philipp Tomsich --- Changes in v2: - add comment for mmc clock div 2 internal - update the commit message drivers/clk/rockchip/clk_rk3036.c | 6 +++--- drivers/clk/rockchip/clk_rk3188.c | 5 +++-- drivers/clk/rockchip/clk_rk322x.c | 8 ++++---- drivers/clk/rockchip/clk_rk3288.c | 1 + drivers/clk/rockchip/clk_rk3328.c | 9 +++++---- drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++---- 6 files changed, 24 insertions(+), 17 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 5ecf512..514ea88 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -235,7 +235,7 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, } src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; - return DIV_TO_RATE(src_rate, div); + return DIV_TO_RATE(src_rate, div) / 2; } static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, @@ -247,10 +247,10 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); /* mmc clock auto divide 2 in internal */ - src_clk_div = (clk_general_rate / 2 + freq - 1) / freq; + src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); if (src_clk_div > 0x7f) { - src_clk_div = (OSC_HZ / 2 + freq - 1) / freq; + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); mux = EMMC_SEL_24M; } else { mux = EMMC_SEL_GPLL; diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 6f30332..cbf31d7 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -287,7 +287,7 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate, return -EINVAL; } - return DIV_TO_RATE(gclk_rate, div); + return DIV_TO_RATE(gclk_rate, div) / 2; } static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate, @@ -296,7 +296,8 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate, int src_clk_div; debug("%s: gclk_rate=%u\n", __func__, gclk_rate); - src_clk_div = RATE_TO_DIV(gclk_rate, freq); + /* mmc clock defaulg div 2 internal, need provide double in cru */ + src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); assert(src_clk_div <= 0x3f); switch (periph) { diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index fdeb816..a1a0aff 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -239,7 +239,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, } src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; - return DIV_TO_RATE(src_rate, div); + return DIV_TO_RATE(src_rate, div) / 2; } static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, @@ -250,11 +250,11 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); - /* mmc clock auto divide 2 in internal */ - src_clk_div = (clk_general_rate / 2 + freq - 1) / freq; + /* mmc clock defaulg div 2 internal, need provide double in cru */ + src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); if (src_clk_div > 0x7f) { - src_clk_div = (OSC_HZ / 2 + freq - 1) / freq; + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); mux = EMMC_SEL_24M; } else { mux = EMMC_SEL_GPLL; diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index adcc0a6..209075a 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -531,6 +531,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, int mux; debug("%s: gclk_rate=%u\n", __func__, gclk_rate); + /* mmc clock defaulg div 2 internal, need provide double in cru */ src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); if (src_clk_div > 0x3f) { diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 2065a8a..c3a6650 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -412,9 +412,9 @@ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT == CLK_EMMC_PLL_SEL_24M) - return DIV_TO_RATE(OSC_HZ, div); + return DIV_TO_RATE(OSC_HZ, div) / 2; else - return DIV_TO_RATE(GPLL_HZ, div); + return DIV_TO_RATE(GPLL_HZ, div) / 2; } static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru, @@ -436,11 +436,12 @@ static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru, return -EINVAL; } /* Select clk_sdmmc/emmc source from GPLL by default */ - src_clk_div = GPLL_HZ / set_rate; + /* mmc clock defaulg div 2 internal, need provide double in cru */ + src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); if (src_clk_div > 127) { /* use 24MHz source for 400KHz clock */ - src_clk_div = OSC_HZ / set_rate; + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); rk_clrsetreg(&cru->clksel_con[con_id], CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 54079cd..d2abda5 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -750,18 +750,21 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) case HCLK_SDMMC: case SCLK_SDMMC: con = readl(&cru->clksel_con[16]); + /* dwmmc controller have internal div 2 */ + div = 2; break; case SCLK_EMMC: con = readl(&cru->clksel_con[21]); + div = 1; break; default: return -EINVAL; } - div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; + div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT == CLK_EMMC_PLL_SEL_24M) - return DIV_TO_RATE(24*1000*1000, div); + return DIV_TO_RATE(OSC_HZ, div); else return DIV_TO_RATE(GPLL_HZ, div); } @@ -776,11 +779,12 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, case HCLK_SDMMC: case SCLK_SDMMC: /* Select clk_sdmmc source from GPLL by default */ - src_clk_div = GPLL_HZ / set_rate; + /* mmc clock defaulg div 2 internal, provide double in cru */ + src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); if (src_clk_div > 127) { /* use 24MHz source for 400KHz clock */ - src_clk_div = 24*1000*1000 / set_rate; + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); rk_clrsetreg(&cru->clksel_con[16], CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |