| Message ID | 1501065662-52029-48-git-send-email-philipp.tomsich@theobroma-systems.com |
|---|---|
| State | Superseded |
| Delegated to: | Philipp Tomsich |
| Headers | show |
On 26 July 2017 at 04:40, Philipp Tomsich <philipp.tomsich@theobroma-systems.com> wrote: > For full SPL support, including DRAM initialisation, we need a few > nodes from the DTS: this commit adds the DMC (DRAM controller) node, > the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU > as 'u-boot,dm-pre-reloc'. In addition to this, we also include the > dt-binding for the DMC to allow DTS files including this DTSI to refer > to the symbolic constants for the DDR3 bin and for the > memory-schedule. > > Note that the DMC contains both the memory regions for the > (Designware) protocol controller as well as the DDR PHY. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > > --- > > Changes in v2: > - removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi > > arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------ > 1 file changed, 19 insertions(+), 6 deletions(-) Reviewed-by: Simon Glass <sjg@chromium.org>
Hi Philipp: On 2017年07月26日 18:40, Philipp Tomsich wrote: > For full SPL support, including DRAM initialisation, we need a few > nodes from the DTS: this commit adds the DMC (DRAM controller) node, > the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU > as 'u-boot,dm-pre-reloc'. In addition to this, we also include the > dt-binding for the DMC to allow DTS files including this DTSI to refer > to the symbolic constants for the DDR3 bin and for the > memory-schedule. > > Note that the DMC contains both the memory regions for the > (Designware) protocol controller as well as the DDR PHY. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > > --- > > Changes in v2: > - removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi > > arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------ > 1 file changed, 19 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi > index 9daf765..163d9ee 100644 > --- a/arch/arm/dts/rk3368.dtsi > +++ b/arch/arm/dts/rk3368.dtsi > @@ -46,6 +46,7 @@ > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/pinctrl/rockchip.h> > #include <dt-bindings/thermal/thermal.h> > +#include <dt-bindings/memory/rk3368-dmc.h> > > / { > compatible = "rockchip,rk3368"; > @@ -227,6 +228,22 @@ > #clock-cells = <0>; > }; > > + dmc: dmc@ff610000 { > + compatible = "rockchip,rk3368-dmc", "syscon"; > + rockchip,cru = <&cru>; > + rockchip,grf = <&grf>; > + rockchip,msch = <&service_msch>; > + reg = <0 0xff610000 0 0x400 > + 0 0xff620000 0 0x400>; > + }; > + > + service_msch: syscon@ffac0000 { > + u-boot,dm-pre-reloc; > + compatible = "rockchip,rk3368-msch", "syscon"; > + reg = <0x0 0xffac0000 0x0 0x2000>; > + status = "okay"; > + }; > + > sdmmc: dwmmc@ff0c0000 { > compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; > reg = <0x0 0xff0c0000 0x0 0x4000>; > @@ -546,12 +563,6 @@ > status = "disabled"; > }; > > - dmc: dmc@ff610000 { > - u-boot,dm-pre-reloc; > - compatible = "rockchip,rk3368-dmc", "syscon"; > - reg = <0x0 0xff610000 0x0 0x1000>; > - }; > - > i2c0: i2c@ff650000 { > compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; > reg = <0x0 0xff650000 0x0 0x1000>; > @@ -653,6 +664,7 @@ > }; > > cru: clock-controller@ff760000 { > + u-boot,dm-pre-reloc; Can we move these u-boot specific properties to rk3368-uboot.dtsi, and keep the core dts/dtsi files the same as the upstream kernel. It will make things easier if we want sync with the upstream kernel someday. > compatible = "rockchip,rk3368-cru"; > reg = <0x0 0xff760000 0x0 0x1000>; > rockchip,grf = <&grf>; > @@ -661,6 +673,7 @@ > }; > > grf: syscon@ff770000 { > + u-boot,dm-pre-reloc; > compatible = "rockchip,rk3368-grf", "syscon"; > reg = <0x0 0xff770000 0x0 0x1000>; > };
Andy, > On 28 Jul 2017, at 10:34, Andy Yan <andy.yan@rock-chips.com> wrote: > > Hi Philipp: > > > On 2017年07月26日 18:40, Philipp Tomsich wrote: >> For full SPL support, including DRAM initialisation, we need a few >> nodes from the DTS: this commit adds the DMC (DRAM controller) node, >> the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU >> as 'u-boot,dm-pre-reloc'. In addition to this, we also include the >> dt-binding for the DMC to allow DTS files including this DTSI to refer >> to the symbolic constants for the DDR3 bin and for the >> memory-schedule. >> >> Note that the DMC contains both the memory regions for the >> (Designware) protocol controller as well as the DDR PHY. >> >> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> >> >> --- >> >> Changes in v2: >> - removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi >> >> arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------ >> 1 file changed, 19 insertions(+), 6 deletions(-) >> >> diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi >> index 9daf765..163d9ee 100644 >> --- a/arch/arm/dts/rk3368.dtsi >> +++ b/arch/arm/dts/rk3368.dtsi >> @@ -46,6 +46,7 @@ >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/pinctrl/rockchip.h> >> #include <dt-bindings/thermal/thermal.h> >> +#include <dt-bindings/memory/rk3368-dmc.h> >> / { >> compatible = "rockchip,rk3368"; >> @@ -227,6 +228,22 @@ >> #clock-cells = <0>; >> }; >> + dmc: dmc@ff610000 { >> + compatible = "rockchip,rk3368-dmc", "syscon"; >> + rockchip,cru = <&cru>; >> + rockchip,grf = <&grf>; >> + rockchip,msch = <&service_msch>; >> + reg = <0 0xff610000 0 0x400 >> + 0 0xff620000 0 0x400>; >> + }; >> + >> + service_msch: syscon@ffac0000 { >> + u-boot,dm-pre-reloc; >> + compatible = "rockchip,rk3368-msch", "syscon"; >> + reg = <0x0 0xffac0000 0x0 0x2000>; >> + status = "okay"; >> + }; >> + >> sdmmc: dwmmc@ff0c0000 { >> compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; >> reg = <0x0 0xff0c0000 0x0 0x4000>; >> @@ -546,12 +563,6 @@ >> status = "disabled"; >> }; >> - dmc: dmc@ff610000 { >> - u-boot,dm-pre-reloc; >> - compatible = "rockchip,rk3368-dmc", "syscon"; >> - reg = <0x0 0xff610000 0x0 0x1000>; >> - }; >> - >> i2c0: i2c@ff650000 { >> compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; >> reg = <0x0 0xff650000 0x0 0x1000>; >> @@ -653,6 +664,7 @@ >> }; >> cru: clock-controller@ff760000 { >> + u-boot,dm-pre-reloc; > > Can we move these u-boot specific properties to rk3368-uboot.dtsi, and keep the core dts/dtsi files > the same as the upstream kernel. It will make things easier if we want sync with the upstream kernel someday. >> compatible = "rockchip,rk3368-cru"; >> reg = <0x0 0xff760000 0x0 0x1000>; >> rockchip,grf = <&grf>; >> @@ -661,6 +673,7 @@ >> }; >> grf: syscon@ff770000 { >> + u-boot,dm-pre-reloc; >> compatible = "rockchip,rk3368-grf", "syscon"; >> reg = <0x0 0xff770000 0x0 0x1000>; >> }; Seems like a missed a couple more of these (as I already started moving these to a '-u-boot.dtsi’ file. I’ll try to catch all of these in the next iteration. Cheers, Philipp.
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 9daf765..163d9ee 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/memory/rk3368-dmc.h> / { compatible = "rockchip,rk3368"; @@ -227,6 +228,22 @@ #clock-cells = <0>; }; + dmc: dmc@ff610000 { + compatible = "rockchip,rk3368-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + service_msch: syscon@ffac0000 { + u-boot,dm-pre-reloc; + compatible = "rockchip,rk3368-msch", "syscon"; + reg = <0x0 0xffac0000 0x0 0x2000>; + status = "okay"; + }; + sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; @@ -546,12 +563,6 @@ status = "disabled"; }; - dmc: dmc@ff610000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3368-dmc", "syscon"; - reg = <0x0 0xff610000 0x0 0x1000>; - }; - i2c0: i2c@ff650000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff650000 0x0 0x1000>; @@ -653,6 +664,7 @@ }; cru: clock-controller@ff760000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>; rockchip,grf = <&grf>; @@ -661,6 +673,7 @@ }; grf: syscon@ff770000 { + u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-grf", "syscon"; reg = <0x0 0xff770000 0x0 0x1000>; };
For full SPL support, including DRAM initialisation, we need a few nodes from the DTS: this commit adds the DMC (DRAM controller) node, the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU as 'u-boot,dm-pre-reloc'. In addition to this, we also include the dt-binding for the DMC to allow DTS files including this DTSI to refer to the symbolic constants for the DDR3 bin and for the memory-schedule. Note that the DMC contains both the memory regions for the (Designware) protocol controller as well as the DDR PHY. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> --- Changes in v2: - removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-)