From patchwork Tue Jul 18 07:29:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 789961 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xBX1q2R0yz9s72 for ; Tue, 18 Jul 2017 17:32:47 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 16236C21DA2; Tue, 18 Jul 2017 07:31:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6214EC21DBD; Tue, 18 Jul 2017 07:29:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8B3F2C21D57; Tue, 18 Jul 2017 07:29:31 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 5BB17C21D57 for ; Tue, 18 Jul 2017 07:29:27 +0000 (UTC) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v6I7OLSM029023; Tue, 18 Jul 2017 09:29:26 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 2brshgwg99-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 18 Jul 2017 09:29:26 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5703F3F; Tue, 18 Jul 2017 07:29:25 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 12524123B; Tue, 18 Jul 2017 07:29:25 +0000 (GMT) Received: from localhost (10.75.127.48) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Tue, 18 Jul 2017 09:29:24 +0200 From: To: , , , Date: Tue, 18 Jul 2017 09:29:09 +0200 Message-ID: <1500362950-30987-9-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1500362950-30987-1-git-send-email-patrice.chotard@st.com> References: <1500362950-30987-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-07-18_04:, , signatures=0 Cc: christophe.kerello@st.com Subject: [U-Boot] [PATCH 8/9] spi: stm32_qspi: add clk_get_rate() support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Replace proprietary clock_get() by clk_get_rate() The stm32_qspi is now "generic" and can be used by other STM32 SoCs. Signed-off-by: Patrice Chotard Acked-by: Vikas MANOCHA --- drivers/spi/stm32_qspi.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index f0434a4..ef2b64e 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -165,6 +165,7 @@ struct stm32_qspi_platdata { struct stm32_qspi_priv { struct stm32_qspi_regs *regs; + ulong clock_rate; u32 max_hz; u32 mode; @@ -471,6 +472,13 @@ static int stm32_qspi_probe(struct udevice *bus) dev_err(bus, "failed to enable clock\n"); return ret; } + + priv->clock_rate = clk_get_rate(&clk); + if (priv->clock_rate < 0) { + clk_disable(&clk); + return priv->clock_rate; + } + #endif setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); @@ -536,7 +544,7 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed) if (speed > plat->max_hz) speed = plat->max_hz; - u32 qspi_clk = clock_get(CLOCK_AHB); + u32 qspi_clk = priv->clock_rate; u32 prescaler = 255; if (speed > 0) { prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;