From patchwork Thu Jul 13 13:49:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrice CHOTARD X-Patchwork-Id: 787758 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3x7chR3Ndwz9s82 for ; Thu, 13 Jul 2017 23:52:39 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2C1CCC21E67; Thu, 13 Jul 2017 13:50:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3F002C21EB4; Thu, 13 Jul 2017 13:49:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AD95DC21DF8; Thu, 13 Jul 2017 13:49:40 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 33F25C21DFF for ; Thu, 13 Jul 2017 13:49:40 +0000 (UTC) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v6DDjbEL017547; Thu, 13 Jul 2017 15:49:38 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 2bp8btghjy-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 13 Jul 2017 15:49:38 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 00CA441; Thu, 13 Jul 2017 13:49:36 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D615C1B8E; Thu, 13 Jul 2017 13:49:36 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Thu, 13 Jul 2017 15:49:36 +0200 From: To: , , , , , Date: Thu, 13 Jul 2017 15:49:19 +0200 Message-ID: <1499953762-3597-4-git-send-email-patrice.chotard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499953762-3597-1-git-send-email-patrice.chotard@st.com> References: <1499953762-3597-1-git-send-email-patrice.chotard@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG5NODE3.st.com (10.75.127.15) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-07-13_07:, , signatures=0 Cc: christophe.kerello@st.com Subject: [U-Boot] [PATCH 3/6] ram: stm32: replace fdtdec_get by ofnode calls X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Patrice Chotard Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..(). This will allow drivers to support a live device tree. Signed-off-by: Patrice Chotard Reviewed-by: Simon Glass --- drivers/ram/stm32_sdram.c | 83 +++++++++++++++++++++++++++-------------------- 1 file changed, 47 insertions(+), 36 deletions(-) diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 6e2c6c7..460e697 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -120,8 +120,8 @@ struct stm32_sdram_timing { struct stm32_sdram_params { struct stm32_fmc_regs *base; u8 no_sdram_banks; - struct stm32_sdram_control sdram_control; - struct stm32_sdram_timing sdram_timing; + struct stm32_sdram_control *sdram_control; + struct stm32_sdram_timing *sdram_timing; u32 sdram_ref_count; }; @@ -133,24 +133,26 @@ int stm32_sdram_init(struct udevice *dev) { struct stm32_sdram_params *params = dev_get_platdata(dev); struct stm32_fmc_regs *regs = params->base; - - writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT - | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT - | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT - | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT - | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT - | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT - | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT - | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT, + struct stm32_sdram_control *control = params->sdram_control; + struct stm32_sdram_timing *timing = params->sdram_timing; + + writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT + | control->cas_latency << FMC_SDCR_CAS_SHIFT + | control->no_banks << FMC_SDCR_NB_SHIFT + | control->memory_width << FMC_SDCR_MWID_SHIFT + | control->no_rows << FMC_SDCR_NR_SHIFT + | control->no_columns << FMC_SDCR_NC_SHIFT + | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT + | control->rd_burst << FMC_SDCR_RBURST_SHIFT, ®s->sdcr1); - writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT - | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT - | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT - | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT - | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT - | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT - | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT, + writel(timing->trcd << FMC_SDTR_TRCD_SHIFT + | timing->trp << FMC_SDTR_TRP_SHIFT + | timing->twr << FMC_SDTR_TWR_SHIFT + | timing->trc << FMC_SDTR_TRC_SHIFT + | timing->tras << FMC_SDTR_TRAS_SHIFT + | timing->txsr << FMC_SDTR_TXSR_SHIFT + | timing->tmrd << FMC_SDTR_TMRD_SHIFT, ®s->sdtr1); writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, @@ -169,7 +171,7 @@ int stm32_sdram_init(struct udevice *dev) FMC_BUSY_WAIT(regs); writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT - | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT) + | control->cas_latency << SDRAM_MODE_CAS_SHIFT) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, ®s->sdcmr); udelay(100); @@ -187,27 +189,36 @@ int stm32_sdram_init(struct udevice *dev) static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) { - int ret; - int node = dev_of_offset(dev); - const void *blob = gd->fdt_blob; + ofnode bank_node; struct stm32_sdram_params *params = dev_get_platdata(dev); - params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1); + params->no_sdram_banks = dev_read_u32_default(dev, "mr-nbanks", 1); debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks); - fdt_for_each_subnode(node, blob, node) { - ret = fdtdec_get_byte_array(blob, node, "st,sdram-control", - (u8 *)¶ms->sdram_control, - sizeof(params->sdram_control)); - if (ret) - return ret; - ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing", - (u8 *)¶ms->sdram_timing, - sizeof(params->sdram_timing)); - if (ret) - return ret; - - params->sdram_ref_count = fdtdec_get_int(blob, node, + dev_for_each_subnode(bank_node, dev) { + params->sdram_control = (struct stm32_sdram_control *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-control", + sizeof(struct stm32_sdram_control)); + + if (!params->sdram_control) { + error("st,sdram-control not found for device: %s", + dev->name); + return -EINVAL; + } + + params->sdram_timing = (struct stm32_sdram_timing *) + ofnode_read_u8_array_ptr(bank_node, + "st,sdram-timing", + sizeof(struct stm32_sdram_timing)); + + if (!params->sdram_timing) { + error("st,sdram-timing not found for device: %s", + dev->name); + return -EINVAL; + } + + params->sdram_ref_count = ofnode_read_u32_default(bank_node, "st,sdram-refcount", 8196); }