From patchwork Wed Jun 21 08:31:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: stefanc@malvell.com X-Patchwork-Id: 778810 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wt3ZV0NlBz9ryv for ; Wed, 21 Jun 2017 22:15:30 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id BDEFDC21C81; Wed, 21 Jun 2017 12:13:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 806A1C21C5B; Wed, 21 Jun 2017 12:12:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9DD5EC21C92; Wed, 21 Jun 2017 08:35:37 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lists.denx.de (Postfix) with ESMTPS id 1ECC3C21C81 for ; Wed, 21 Jun 2017 08:35:36 +0000 (UTC) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v5L8UPRS017560; Wed, 21 Jun 2017 01:35:33 -0700 Received: from il-exch01.marvell.com ([199.203.130.101]) by mx0a-0016f401.pphosted.com with ESMTP id 2b6cq7pwb8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2017 01:35:33 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by IL-EXCH01.marvell.com (10.4.102.220) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 21 Jun 2017 11:35:30 +0300 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 21 Jun 2017 01:35:30 -0700 Received: from stefanc.pt.marvell.com (unknown [10.5.24.120]) by maili.marvell.com (Postfix) with ESMTP id 8E3093F703F; Wed, 21 Jun 2017 01:35:28 -0700 (PDT) From: To: Date: Wed, 21 Jun 2017 11:31:36 +0300 Message-ID: <1498033898-15650-9-git-send-email-stefanc@malvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498033898-15650-1-git-send-email-stefanc@malvell.com> References: <1498033898-15650-1-git-send-email-stefanc@malvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-21_01:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706210143 X-Mailman-Approved-At: Wed, 21 Jun 2017 12:12:02 +0000 Cc: stefanc@malvell.com, joe.hershberger@ni.com, sr@denx.de, igall@marvell.com Subject: [U-Boot] [PATCH 08/10] net: mvpp2x: Set BM pool high address X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Chulski MVPP22 driver support 64 Bit arch and require BM pool high address configuration. Change-Id: I04417b8cc081ea75e43b230d5ba1cc5c0071ce25 Signed-off-by: Stefan Chulski Reviewed-on: http://vgitil04.il.marvell.com:8080/39967 Tested-by: iSoC Platform CI Reviewed-by: Nadav Haklai Reviewed-on: http://vgitil04.il.marvell.com:8080/39953 Reviewed-by: Igal Liberman Acked-by: Joe Hershberger --- drivers/net/mvpp2.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 2cdf934..931047e 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -322,6 +322,8 @@ do { \ #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 #define MVPP22_BM_MC_RLS_REG 0x64d4 +#define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310 +#define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff /* TX Scheduler registers */ #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 @@ -2602,6 +2604,10 @@ static int mvpp2_bm_pool_create(struct udevice *dev, mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), lower_32_bits(bm_pool->dma_addr)); + if (priv->hw_version == MVPP22) + mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG, + (upper_32_bits(bm_pool->dma_addr) & + MVPP22_BM_POOL_BASE_HIGH_MASK)); mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));