From patchwork Wed Jun 21 08:31:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: stefanc@malvell.com X-Patchwork-Id: 778812 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wt3cT70ccz9ryv for ; Wed, 21 Jun 2017 22:17:13 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B4BC2C21CB4; Wed, 21 Jun 2017 12:14:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5C47DC21C7D; Wed, 21 Jun 2017 12:12:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BCE51C21C64; Wed, 21 Jun 2017 08:35:32 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lists.denx.de (Postfix) with ESMTPS id 7FB94C21C97 for ; Wed, 21 Jun 2017 08:35:27 +0000 (UTC) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v5L8TWWi004635; Wed, 21 Jun 2017 01:35:25 -0700 Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2b6bsxuwp4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2017 01:35:25 -0700 Received: from IL-EXCH03.marvell.com (10.5.102.220) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 21 Jun 2017 01:35:23 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by IL-EXCH03.marvell.com (10.5.102.220) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 21 Jun 2017 11:35:20 +0300 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 21 Jun 2017 01:35:20 -0700 Received: from stefanc.pt.marvell.com (unknown [10.5.24.120]) by maili.marvell.com (Postfix) with ESMTP id 5F4293F7040; Wed, 21 Jun 2017 01:35:18 -0700 (PDT) From: To: Date: Wed, 21 Jun 2017 11:31:33 +0300 Message-ID: <1498033898-15650-6-git-send-email-stefanc@malvell.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498033898-15650-1-git-send-email-stefanc@malvell.com> References: <1498033898-15650-1-git-send-email-stefanc@malvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-21_01:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 impostorscore=0 adultscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706210143 X-Mailman-Approved-At: Wed, 21 Jun 2017 12:12:02 +0000 Cc: stefanc@malvell.com, joe.hershberger@ni.com, sr@denx.de, igall@marvell.com Subject: [U-Boot] [PATCH 05/10] net: mvpp2x: decrease size of AGGR_TXQ and CPU_DESC_CHUNK X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Chulski U-boot use single physical tx queue with size 16 descriptors. So aggregated tx queue size should be equal to physical tx queue and cpu descriptor chunk(number of descriptors delivered from physical tx queue to aggregated tx queue by one chunk) shouldn't be larger than physical tx queue. Fix: Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as physical TXQ. Change-Id: I22c759a9bcf533ecddbdc495cd48d72e8761764e Signed-off-by: Stefan Chulski Reviewed-on: http://vgitil04.il.marvell.com:8080/39964 Tested-by: iSoC Platform CI Reviewed-by: Nadav Haklai Reviewed-on: http://vgitil04.il.marvell.com:8080/39658 Reviewed-by: Igal Liberman Acked-by: Joe Hershberger --- drivers/net/mvpp2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index af3c3ef..901e9d8 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -623,10 +623,10 @@ enum mv_netc_lanes { #define MVPP2_MAX_TXD 16 /* Amount of Tx descriptors that can be reserved at once by CPU */ -#define MVPP2_CPU_DESC_CHUNK 64 +#define MVPP2_CPU_DESC_CHUNK 16 /* Max number of Tx descriptors in each aggregated queue */ -#define MVPP2_AGGR_TXQ_SIZE 256 +#define MVPP2_AGGR_TXQ_SIZE 16 /* Descriptor aligned size */ #define MVPP2_DESC_ALIGNED_SIZE 32