From patchwork Tue Jun 20 03:56:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: eric.gao@rock-chips.com X-Patchwork-Id: 778102 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wsDYp6PD5z9s0g for ; Tue, 20 Jun 2017 13:57:01 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2DC4CC21CC3; Tue, 20 Jun 2017 03:56:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 44D19C21C1F; Tue, 20 Jun 2017 03:56:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7F15DC21C1F; Tue, 20 Jun 2017 03:56:44 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.138]) by lists.denx.de (Postfix) with ESMTPS id 74933C21BE6 for ; Tue, 20 Jun 2017 03:56:43 +0000 (UTC) Received: from eric.gao?rock-chips.com (unknown [192.168.165.252]) by regular1.263xmail.com (Postfix) with ESMTP id 90D7F79D1; Tue, 20 Jun 2017 11:56:38 +0800 (CST) X-263anti-spam: X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ABS-CHECKED: 4 Received: from localhost (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 26CFA3F2; Tue, 20 Jun 2017 11:56:35 +0800 (CST) X-RL-SENDER: eric.gao@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: eric.gao@rock-chips.com X-UNIQUE-TAG: <0c0baadd30ba0cbee3e92515423e43de> X-ATTACHMENT-NUM: 0 X-SENDER: eric.gao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost (unknown [103.29.142.67]) by smtp.263.net (Postfix) whith ESMTP id 27674J41WPJ; Tue, 20 Jun 2017 11:56:37 +0800 (CST) From: Eric Gao To: sjg@chromium.org Date: Tue, 20 Jun 2017 11:56:34 +0800 Message-Id: <1497930994-5582-1-git-send-email-eric.gao@rock-chips.com> X-Mailer: git-send-email 1.9.1 Cc: u-boot@lists.denx.de, eric.gao@rock-chips.com Subject: [U-Boot] [PATCH v3] rockchip: video: mipi: Modify variable type for arm32 compatibility X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some address relevant varibable is defined originally as u64. To compatible with arm32, this patch change them to uintptr_t type. Signed-off-by: Eric Gao Reviewed-by: Simon Glass --- Changes in v2: -Change the address base variable from "uintptr_t *" to "uintptr_t" Changes in v1: -Change the address base variable to uintptr_t * type. drivers/video/rockchip/rk_mipi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index ad00397..521256e 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; * @txesc_clk: clock for tx esc mode */ struct rk_mipi_priv { - void __iomem *regs; + uintptr_t regs; struct rk3399_grf_regs *grf; struct udevice *panel; struct mipi_dsi *dsi; @@ -76,13 +76,13 @@ static int rk_mipi_read_timing(struct udevice *dev, * use define in rk_mipi.h directly for this parameter * @val: value that will be write to specified bits of register */ -static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val) +static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val) { u32 dat; u32 mask; u32 offset = (reg >> OFFSET_SHIFT) & 0xff; u32 bits = (reg >> BITS_SHIFT) & 0xff; - u64 addr = (reg >> ADDR_SHIFT) + regs; + uintptr_t *addr = (reg >> ADDR_SHIFT) + regs; /* Mask for specifiled bits,the corresponding bits will be clear */ mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits))); @@ -108,7 +108,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, int node, timing_node; int val; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + uintptr_t regs = priv->regs; struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); u32 txbyte_clk = priv->txbyte_clk; u32 txesc_clk = priv->txesc_clk; @@ -224,7 +224,7 @@ static int rk_mipi_dsi_enable(struct udevice *dev, } /* rk mipi dphy write function. It is used to write test data to dphy */ -static void rk_mipi_phy_write(u32 regs, unsigned char test_code, +static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code, unsigned char *test_data, unsigned char size) { int i = 0; @@ -253,7 +253,7 @@ static int rk_mipi_phy_enable(struct udevice *dev) { int i; struct rk_mipi_priv *priv = dev_get_priv(dev); - u64 regs = (u64)priv->regs; + uintptr_t regs = priv->regs; u64 fbdiv; u64 prediv = 1; u32 max_fbdiv = 512;