From patchwork Tue Jun 13 09:29:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 775033 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wn4Xx4Vb7z9s2s for ; Tue, 13 Jun 2017 19:41:52 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Z9/u83+q"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id 6611FC21CDD; Tue, 13 Jun 2017 09:41:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7B251C21D6D; Tue, 13 Jun 2017 09:30:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A9075C21D59; Tue, 13 Jun 2017 09:30:35 +0000 (UTC) Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by lists.denx.de (Postfix) with ESMTPS id E8B24C21CC8 for ; Tue, 13 Jun 2017 09:30:23 +0000 (UTC) Received: by mail-pg0-f65.google.com with SMTP id v18so17411439pgb.3 for ; Tue, 13 Jun 2017 02:30:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=jYJttElnD8symOwr32hczX8ALtkXWwGKGLXVcVHu7JM=; b=Z9/u83+qHdPWdPx75uHS9Pr/urIkm+tB4qGqLUMjqTSVZbXnq+Ht8rhLAZafPM6uAG yzwehuhM+I4q/UlG7ekoAg3l4wjHynLybbzDSZguYFB4/esSpKmqsD3Xin0HxKLukeXx rfk4+X1aOeC/FDDNfLMVvryH6bfojX88hBXa2YuATO392+EJneEmainxcktwxMlIyjYu t4khpuOczGPA5Lpg09qj8chQBl/dZHuUEZ9Ycb5/JHTLWd4zx/QAn2jL3/2LqMlFnQQU HGYLldf8ImKiB/j7Dd7A+0BJb38DRg+1HlPhAIkFfLwe084tFDEA6EepPzEzUawezp1Y Xdtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=jYJttElnD8symOwr32hczX8ALtkXWwGKGLXVcVHu7JM=; b=USf+RD9B/iDZkQTPP7cUE+2LQIoD1LkqbZLGzy2YQXRQdy8iAhKU2tflVUG9y3jyse B6Y7hvSFWhF1Hn0wr5FB3g5oeaOwK+GEwwSO+mEnmxXULz+3Uq1GyeDLEJzNHmc+kSUB CLYmBTRZ8aMYeIEfNNMrAg2+XzRUbZPeZn9Cq25QFXtrnutU6AxrdGs+NKW2Vc1VkMwK PIoOdbYR9UmpFT+s9GH5AfSplNM1i8H5+RSeTgleTIShX/zqz2xyUlvIjo6OJUavFhE/ +8FTKtn/SV5jEBIIjSGsTC9Cgz93Mqfa0SFfTnRFd8ecxxQjdq8zy1GwsAsYnvFCaUjz 5qZg== X-Gm-Message-State: AODbwcDV0IFbHESTpxd3OZnWzUgzJxcdPKroCZ4BDcFbsNF3IK3MR/c4 z4E07zjvcBlZkQ== X-Received: by 10.98.12.134 with SMTP id 6mr35859908pfm.5.1497346222610; Tue, 13 Jun 2017 02:30:22 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id h71sm14677837pfk.126.2017.06.13.02.30.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Jun 2017 02:30:22 -0700 (PDT) From: Kever Yang To: sjg@chromium.org Date: Tue, 13 Jun 2017 17:29:59 +0800 Message-Id: <1497346202-774-5-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497346202-774-1-git-send-email-kever.yang@rock-chips.com> References: <1497346202-774-1-git-send-email-kever.yang@rock-chips.com> Cc: u-boot@lists.denx.de, Andy Yan , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [U-Boot] [PATCH 4/7] rockchip: rk3368: add sdram driver for U-Boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add sdram driver in U-Boot for get the correct sdram size from sys_reg, so that U-Boot can co-work with Rockchip loader or SPL to get different dram capability and then tell the kernel. Signed-off-by: Kever Yang Reviewed-by: Simon Glass --- arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 4 +- arch/arm/mach-rockchip/rk3368/Makefile | 1 + arch/arm/mach-rockchip/rk3368/sdram_rk3368.c | 66 +++++++++++++++++++++++++ 3 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h index 3233dc3..93c4e7d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -92,8 +92,10 @@ struct rk3368_pmu_grf { u32 gpio0d_drv; u32 gpio0l_sr; u32 gpio0h_sr; + u32 reserved[(0x200 - 0x34) / 4 - 1]; + u32 os_reg[4]; }; -check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); +check_member(rk3368_pmu_grf, os_reg[3], 0x20c); /*GRF_GPIO0C_IOMUX*/ enum { diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile index 46798c2..0390716 100644 --- a/arch/arm/mach-rockchip/rk3368/Makefile +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -5,4 +5,5 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o +obj-y += sdram_rk3368.o obj-y += syscon_rk3368.o diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c new file mode 100644 index 0000000..378734c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +struct dram_info { + struct ram_info info; + struct rk3368_pmu_grf *pmugrf; +}; + +static int rk3368_dmc_probe(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); + debug("%s: grf=%p\n", __func__, priv->pmugrf); + priv->info.base = 0; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->pmugrf->os_reg[2]); + /* + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is + * inaccessible for some IP controller. + */ + priv->info.size = min(priv->info.size, 0xfe000000); + + return 0; +} + +static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3368_dmc_ops = { + .get_info = rk3368_dmc_get_info, +}; + + +static const struct udevice_id rk3368_dmc_ids[] = { + { .compatible = "rockchip,rk3368-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3368) = { + .name = "rockchip_rk3368_dmc", + .id = UCLASS_RAM, + .of_match = rk3368_dmc_ids, + .ops = &rk3368_dmc_ops, + .probe = rk3368_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +};