From patchwork Thu Jun 8 07:48:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Lothar_Wa=C3=9Fmann?= X-Patchwork-Id: 772899 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wjyH80VMSz9s78 for ; Thu, 8 Jun 2017 17:49:07 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B2FB9C21CE7; Thu, 8 Jun 2017 07:49:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6742EC21CE7; Thu, 8 Jun 2017 07:48:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0E34DC21CE7; Thu, 8 Jun 2017 07:48:58 +0000 (UTC) Received: from smtprelay09.ispgateway.de (smtprelay09.ispgateway.de [134.119.228.114]) by lists.denx.de (Postfix) with ESMTPS id B2B56C21C26 for ; Thu, 8 Jun 2017 07:48:57 +0000 (UTC) Received: from [89.1.81.74] (helo=ipc1.ka-ro) by smtprelay09.ispgateway.de with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.89) (envelope-from ) id 1dIsBb-0002BZ-Dx; Thu, 08 Jun 2017 09:48:55 +0200 Received: from lothar by ipc1.ka-ro with local (Exim 4.84_2 #2 (Debian)) id 1dIsBa-0003zC-CO; Thu, 08 Jun 2017 09:48:54 +0200 From: =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= To: Albert Aribaud , Alexander Graf , Heiko Schocher , Keerthy , Simon Glass , Stefan Agner , u-boot@lists.denx.de, =?UTF-8?q?Lothar=20Wa=C3=9Fmann?= Date: Thu, 8 Jun 2017 09:48:41 +0200 Message-Id: <1496908121-15028-1-git-send-email-LW@KARO-electronics.de> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 X-Df-Sender: bHdAa2Fyby1lbGVjdHJvbmljcy5kZQ== Subject: [U-Boot] [PATCH] ARM: remove bogus cp_delay() function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The cp_delay() function was introduced because of a missing 'volatile' attribute to the 'asm' statement in get_cr() which led to the 'mrc' instruction in get_cr() being optimised out eventually. This has been fixed in commit 53fd4b8c22bb ("arm: mmu: Add missing volatile for reading SCTLR register") but the bogus cp_delay() function which was introduced as a workaround for the malfunctioning get_cr() was never removed. Signed-off-by: Lothar Waßmann Reviewed-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/lib/cache-cp15.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index e9bbcf5..2334edb 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -22,16 +22,6 @@ __weak void arm_init_domains(void) { } -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); - asm volatile("" : : : "memory"); -} - void set_section_dcache(int section, enum dcache_option option) { #ifdef CONFIG_ARMV7_LPAE @@ -196,7 +186,6 @@ static inline void mmu_setup(void) /* and enable the mmu */ reg = get_cr(); /* get control reg. */ - cp_delay(); set_cr(reg | CR_M); } @@ -214,7 +203,6 @@ static void cache_enable(uint32_t cache_bit) if ((cache_bit == CR_C) && !mmu_enabled()) mmu_setup(); reg = get_cr(); /* get control reg. */ - cp_delay(); set_cr(reg | cache_bit); } @@ -224,7 +212,6 @@ static void cache_disable(uint32_t cache_bit) uint32_t reg; reg = get_cr(); - cp_delay(); if (cache_bit == CR_C) { /* if cache isn;t enabled no need to disable */ @@ -234,7 +221,7 @@ static void cache_disable(uint32_t cache_bit) cache_bit |= CR_M; } reg = get_cr(); - cp_delay(); + if (cache_bit == (CR_C | CR_M)) flush_dcache_all(); set_cr(reg & ~cache_bit);