From patchwork Wed May 31 16:16:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 769247 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wdG065p1Nz9s7C for ; Thu, 1 Jun 2017 02:19:50 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 8DAB1C21CDA; Wed, 31 May 2017 16:19:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DE364C21CB8; Wed, 31 May 2017 16:16:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BCBF7C21C69; Wed, 31 May 2017 16:16:51 +0000 (UTC) Received: from mail.theobroma-systems.com (vegas.theobroma-systems.com [144.76.126.164]) by lists.denx.de (Postfix) with ESMTPS id 7F414C21C69 for ; Wed, 31 May 2017 16:16:47 +0000 (UTC) Received: from [86.59.122.178] (port=40356 helo=android.lan) by mail.theobroma-systems.com with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1dG6If-00050s-IT; Wed, 31 May 2017 18:16:45 +0200 From: Philipp Tomsich To: u-boot@lists.denx.de Date: Wed, 31 May 2017 18:16:37 +0200 Message-Id: <1496247397-744-4-git-send-email-philipp.tomsich@theobroma-systems.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496247397-744-1-git-send-email-philipp.tomsich@theobroma-systems.com> References: <1496247397-744-1-git-send-email-philipp.tomsich@theobroma-systems.com> Cc: Philipp Tomsich , Klaus Goger , Lin huang Subject: [U-Boot] [PATCH 4/4] rockchip: dts: rk3399-puma: select DRAM timing via Kconfig X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The RK3399-Q7 has multiple build-options for its DRAM configuration, including the timing of the DRAM components populated. While DDR3-1600 is the standard configuration, custom-configurations are available with DDR3-1333 (for a further cost-optimisation) and with DDR3-1866 (as a premium option). To simplify our test automation (without the need to maintain 3 different defconfigs) and customer evaluation, we make this selectable via Kconfig. Signed-off-by: Philipp Tomsich Reviewed-by: Simon Glass --- arch/arm/dts/rk3399-puma.dts | 8 +++++++ board/theobroma-systems/puma_rk3399/Kconfig | 37 +++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts index fca14d3..41d32eb 100644 --- a/arch/arm/dts/rk3399-puma.dts +++ b/arch/arm/dts/rk3399-puma.dts @@ -8,7 +8,15 @@ #include #include "rk3399.dtsi" +#if defined(CONFIG_SYS_TSD_PUMA_DDR3_1333) +#include "rk3399-sdram-ddr3-1333.dtsi" +#elif defined(CONFIG_SYS_TSD_PUMA_DDR3_1600) #include "rk3399-sdram-ddr3-1600.dtsi" +#elif defined(CONFIG_SYS_TSD_PUMA_DDR3_1866) +#include "rk3399-sdram-ddr3-1866.dtsi" +#else +#error "Unknown memory timing configuration for the RK3399-Q7" +#endif / { model = "Theobroma Systems RK3399-Q7 SoM"; diff --git a/board/theobroma-systems/puma_rk3399/Kconfig b/board/theobroma-systems/puma_rk3399/Kconfig index a645590..1773648 100644 --- a/board/theobroma-systems/puma_rk3399/Kconfig +++ b/board/theobroma-systems/puma_rk3399/Kconfig @@ -12,4 +12,41 @@ config SYS_CONFIG_NAME config BOARD_SPECIFIC_OPTIONS # dummy def_bool y +if SPL + +choice + prompt "RK3399-Q7 DRAM timings" + default SYS_TSD_PUMA_DDR3_1600 + help + The RK3399-Q7 module is orderable in multiple memory + configurations, which may also differ in the timings used. + + DDR3-1600 is the standard configuration, but both DDR3-1333 + (for potential cost-optimisation) and DDR3-1866 (as a + premium option) are fully validated in the design. + + The setting of this option is used to select the appropriate + timings for inclusion in the device tree controlling DRAM + initialisation during the board-initialisation performed by + the SPL stage. + +config SYS_TSD_PUMA_DDR3_1333 + bool "DDR3-1333 timings" + help + Use DDR3-1333 timings for the DRAM setup of the RK3399-Q7. + +config SYS_TSD_PUMA_DDR3_1600 + bool "DDR3-1600 timings" + help + Use DDR3-1600 timings for the DRAM setup of the RK3399-Q7. + +config SYS_TSD_PUMA_DDR3_1866 + bool "DDR3-1866 timings" + help + Use DDR3-1866 timings for the DRAM setup of the RK3399-Q7. + +endchoice + +endif + endif