From patchwork Wed May 31 08:04:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 768941 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wd2xl26j7z9s89 for ; Wed, 31 May 2017 18:02:03 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P4/DVaIP"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id EA367C21C5A; Wed, 31 May 2017 08:00:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AD552C21C68; Wed, 31 May 2017 08:00:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AE273C21C8B; Wed, 31 May 2017 08:00:10 +0000 (UTC) Received: from mail-qt0-f194.google.com (mail-qt0-f194.google.com [209.85.216.194]) by lists.denx.de (Postfix) with ESMTPS id 14140C21C71 for ; Wed, 31 May 2017 08:00:05 +0000 (UTC) Received: by mail-qt0-f194.google.com with SMTP id r58so1016626qtb.2 for ; Wed, 31 May 2017 01:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B+JIIRuhPmiFmW8ajcsXMmhhy6bdh+bYUKxJhgZSsrI=; b=P4/DVaIPN8B3g5nx9FrJhlYbV0CKxFwzfYFWcnkKn+OV0CoETtyfrkyzLDa+O0JHRA xTHrTK7rFmSD0c9+6cqQK7lZXkp1hFjq77LqtvWZbWd60qdq9ma1tqJ6Y8e1o+ciPDjk xnpA5thWthSUqjICG3MfzQEQIVFlOIPYaheccUBKfmbrg0PH2dVEqQ+44xbGWnmpblXh nOa8RMgSJdAGGLMEMthlTvEwQOrjVXodT6+Px/cuLUdybEOsCYcWx4lGgq/UbeAQzB8v OmsRG163vw0duVOHxJL7wjYVr9XGGPZmn+4wL3daoAvk4nF6UmaN3J3H5MnVddfrfsXY RSxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B+JIIRuhPmiFmW8ajcsXMmhhy6bdh+bYUKxJhgZSsrI=; b=l9CLyd+QZRnLU6rvP4rnP7m04hT0QkC+FjXFiwZlLDmTV6JcSrZ7yAdt13Q7grzdSs r+jTJwXWVplLXzr7VMScsPmblhDESVbKKKgfork6jIsX6iDUEe8h1w3rRDIpS/k1Sgzb 3W35Vou/kzhe4O8EW5HjG0V7JdQahzYpgg41P2UG7unO+PK0dbBKBixOgAhSPdw6LXlf ofMlvXy9zJP2tcY+RrpEDb+G2cY1zfOgWWmuJKS7e1F4OGHS45w+wxneKIjT98A7GRZ0 xQ6HnyBt7/rsWvb7fAwk41+SNpP2ztZHBkaSRs5354tKhC8CGwLOGE6q6v5KiSGJN5B3 o8kA== X-Gm-Message-State: AODbwcCxU/yq6nLquHqscxQjZfKIAqfYzvAHjOsXqwTCMy/73UOyNjtu 5Fr3YqQn/gclAg== X-Received: by 10.237.59.119 with SMTP id q52mr31221636qte.143.1496217604073; Wed, 31 May 2017 01:00:04 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id s7sm9968891qtb.35.2017.05.31.01.00.02 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 May 2017 01:00:03 -0700 (PDT) From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Wed, 31 May 2017 01:04:15 -0700 Message-Id: <1496217855-8745-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1496217855-8745-1-git-send-email-bmeng.cn@gmail.com> References: <1496217855-8745-1-git-send-email-bmeng.cn@gmail.com> Cc: Stefan Roese Subject: [U-Boot] [PATCH 4/4] x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present lpe/lpss-sio/scc FSP properties are all boolean, but in fact for "enable-lpe" it has 3 possible options. This adds macros for these options and change the property from a boolean type to an integer type, and change their names to explicitly indicate what the property is really for. Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- arch/x86/cpu/baytrail/fsp_configs.c | 11 ++++++----- arch/x86/dts/bayleybay.dts | 6 +++--- arch/x86/dts/baytrail_som-db5800-som-6867.dts | 4 ++-- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 6 +++--- arch/x86/dts/dfi-bt700.dtsi | 6 +++--- arch/x86/dts/minnowmax.dts | 6 +++--- arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h | 10 ++++++++++ arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h | 6 +++--- doc/device-tree-bindings/misc/intel,baytrail-fsp.txt | 12 ++++++------ 9 files changed, 39 insertions(+), 28 deletions(-) diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index c48ac07..45f9bf9 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -175,9 +175,10 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, "fsp,enable-azalia"); fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); - fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe"); - fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node, - "fsp,lpss-sio-enable-pci-mode"); + fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode", + LPE_MODE_PCI); + fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode", + LPSS_SIO_MODE_PCI); fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0"); fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1"); fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0"); @@ -199,8 +200,8 @@ void update_fsp_configs(struct fsp_config_data *config, fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, "fsp,mrc-debug-msg"); fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); - fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node, - "fsp,scc-enable-pci-mode"); + fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode", + SCC_MODE_PCI); fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node, "fsp,igd-render-standby"); fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node, diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index a577b93..0c314e0 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -248,8 +248,8 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -264,7 +264,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts index 3fc36f1..171e7ff 100644 --- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -268,7 +268,7 @@ fsp,enable-sata; fsp,sata-mode = ; fsp,enable-azalia; - fsp,lpss-sio-enable-pci-mode; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -283,7 +283,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,enable-igd; }; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 369cea6..ae11ccc 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -258,8 +258,8 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-pwm0; @@ -267,7 +267,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index 33f2a9c..04aa95a 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -261,8 +261,8 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -277,7 +277,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index a4e2fa2..4c0a8fe 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -272,8 +272,8 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -288,7 +288,7 @@ fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>; diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h index 382cb79..1c6c247 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h @@ -93,4 +93,14 @@ struct fspinit_rtbuf { #define DIMM_SIDES_1RANKS 0 #define DIMM_SIDES_2RANKS 1 +#define LPE_MODE_DISABLED 0 +#define LPE_MODE_PCI 1 +#define LPE_MODE_ACPI 2 + +#define LPSS_SIO_MODE_ACPI 0 +#define LPSS_SIO_MODE_PCI 1 + +#define SCC_MODE_ACPI 0 +#define SCC_MODE_PCI 1 + #endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h index b083b6e..8c07b37 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -47,8 +47,8 @@ struct __packed upd_region { uint8_t enable_azalia; /* Offset 0x002f */ uint32_t azalia_config_ptr; /* Offset 0x0030 */ uint8_t enable_xhci; /* Offset 0x0034 */ - uint8_t enable_lpe; /* Offset 0x0035 */ - uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */ + uint8_t lpe_mode; /* Offset 0x0035 */ + uint8_t lpss_sio_mode; /* Offset 0x0036 */ uint8_t enable_dma0; /* Offset 0x0037 */ uint8_t enable_dma1; /* Offset 0x0038 */ uint8_t enable_i2_c0; /* Offset 0x0039 */ @@ -67,7 +67,7 @@ struct __packed upd_region { uint8_t reserved2[5]; /* Offset 0x0046 */ uint8_t mrc_debug_msg; /* Offset 0x004b */ uint8_t isp_enable; /* Offset 0x004c */ - uint8_t scc_enable_pci_mode; /* Offset 0x004d */ + uint8_t scc_mode; /* Offset 0x004d */ uint8_t igd_render_standby; /* Offset 0x004e */ uint8_t txe_uma_enable; /* Offset 0x004f */ uint8_t os_selection; /* Offset 0x0050 */ diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt index 691ae53..929ae88 100644 --- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt +++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt @@ -19,8 +19,6 @@ is matched up to Intel's E3800 FSPv4 release. - fsp,enable-sata - fsp,enable-azalia - fsp,enable-xhci -- fsp,enable-lpe -- fsp,lpss-sio-enable-pci-mode - fsp,enable-dma0 - fsp,enable-dma1 - fsp,enable-i2-c0 @@ -35,7 +33,6 @@ is matched up to Intel's E3800 FSPv4 release. - fsp,enable-hsi - fsp,mrc-debug-msg - fsp,isp-enable -- fsp,scc-enable-pci-mode - fsp,igd-render-standby - fsp,txe-uma-enable - fsp,emmc45-ddr50-enabled @@ -57,9 +54,12 @@ discovered by the FSP and used to setup main memory. - fsp,mrc-init-spd-addr2 - fsp,emmc-boot-mode - fsp,sata-mode +- fsp,lpe-mode +- fsp,lpss-sio-mode - fsp,igd-dvmt50-pre-alloc - fsp,aperture-size - fsp,gtt-size +- fsp,scc-mode - fsp,os-selection - fsp,emmc45-retune-timer-value @@ -110,8 +110,8 @@ Example (from MinnowMax Dual Core): fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = ; - fsp,enable-lpe; - fsp,lpss-sio-enable-pci-mode; + fsp,lpe-mode = ; + fsp,lpss-sio-mode = ; fsp,enable-dma0; fsp,enable-dma1; fsp,enable-i2c0; @@ -126,7 +126,7 @@ Example (from MinnowMax Dual Core): fsp,igd-dvmt50-pre-alloc = ; fsp,aperture-size = ; fsp,gtt-size = ; - fsp,scc-enable-pci-mode; + fsp,scc-mode = ; fsp,os-selection = ; fsp,emmc45-ddr50-enabled; fsp,emmc45-retune-timer-value = <8>;