From patchwork Sun May 28 19:55:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas MANOCHA X-Patchwork-Id: 767954 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wbWRL0C7Xz9s2Q for ; Mon, 29 May 2017 06:18:53 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id B59B9C21C40; Sun, 28 May 2017 20:18:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AD91BC21C57; Sun, 28 May 2017 20:17:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C4ADEC21C3C; Sun, 28 May 2017 20:17:40 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 60435C21C6E for ; Sun, 28 May 2017 20:17:37 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v4SKH8Js025833; Sun, 28 May 2017 22:17:36 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-.pphosted.com with ESMTP id 2apy7q06yr-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 28 May 2017 22:17:36 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BA67131; Sun, 28 May 2017 20:17:35 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag7node3.st.com [10.75.127.21]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9F1172414; Sun, 28 May 2017 20:17:35 +0000 (GMT) Received: from localhost (10.75.127.48) by SFHDAG7NODE3.st.com (10.75.127.21) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Sun, 28 May 2017 22:17:34 +0200 From: Vikas Manocha To: Date: Sun, 28 May 2017 12:55:12 -0700 Message-ID: <1496001329-30038-6-git-send-email-vikas.manocha@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496001329-30038-1-git-send-email-vikas.manocha@st.com> References: <1496001329-30038-1-git-send-email-vikas.manocha@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.48] X-ClientProxiedBy: SFHDAG8NODE3.st.com (10.75.127.24) To SFHDAG7NODE3.st.com (10.75.127.21) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-28_15:, , signatures=0 Cc: christophe.kerello@st.com, alexandre.torgue@st.com, christophe.priouzeau@st.com, Toshifumi NISHINAGA Subject: [U-Boot] [PATCH v2 5/7] serial: stm32f7: disable overrun X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" With overrun enabled, serial port console freezes & stops receiving data with overun error if we keep sending data. Signed-off-by: Vikas Manocha --- Changed in v2: None drivers/serial/serial_stm32x7.c | 3 +++ drivers/serial/serial_stm32x7.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c index 1907cef..2b305cd 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32x7.c @@ -93,6 +93,9 @@ static int stm32_serial_probe(struct udevice *dev) } #endif + /* Disable usart-> disable overrun-> enable usart */ + clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); + setbits_le32(&usart->cr3, USART_CR3_OVRDIS); setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); return 0; diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h index 6190d67..8c02548 100644 --- a/drivers/serial/serial_stm32x7.h +++ b/drivers/serial/serial_stm32x7.h @@ -27,6 +27,8 @@ struct stm32_usart { #define USART_CR1_TE (1 << 3) #define USART_CR1_UE (1 << 0) +#define USART_CR3_OVRDIS (1 << 12) + #define USART_SR_FLAG_RXNE (1 << 5) #define USART_SR_FLAG_TXE (1 << 7)