From patchwork Fri May 5 03:01:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 758843 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wJxWc0YQgz9s9c for ; Fri, 5 May 2017 13:02:04 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GnUIcL0o"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id C5496C21C52; Fri, 5 May 2017 03:01:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BC043C21BE6; Fri, 5 May 2017 03:01:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 85492C21BE6; Fri, 5 May 2017 03:01:53 +0000 (UTC) Received: from mail-pg0-f67.google.com (mail-pg0-f67.google.com [74.125.83.67]) by lists.denx.de (Postfix) with ESMTPS id D8B6AC21BE5 for ; Fri, 5 May 2017 03:01:52 +0000 (UTC) Received: by mail-pg0-f67.google.com with SMTP id u187so527487pgb.1 for ; Thu, 04 May 2017 20:01:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=bbCBRhQw3WQKD4rtR8i52cKJbIR54RIkp78OvYxafaw=; b=GnUIcL0oHMtiWfuzaVO5p3DLoJ47o1nrrKcABMWbMoAVrS3CrGZH59YrKhJM5MpgkI PVRAM563iB0xziWhkgLNWlbcYbRnk5Y5j3sb8CwlWCffG5o0jO1F024bvCxWbh7aG+2Z cTjEtHNEuJ1YfbNgLEUhYiZ3XUaycVTdqALIynt0FVmYmKhEmIjNItqtSQz+0hWbmRAY Hxu/G1S9a+nvCZN02AI4ciwfZSdi2eziiueAD7iOeN8Ps1j7qVTws8DPokKn7yTciSSO qWwWE0RYvesJD2vlmvw9KrqxKAXmVIM9vL79y5MOrjGY8adFt4GI8xNckF1Re4lwMYXF 2+Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=bbCBRhQw3WQKD4rtR8i52cKJbIR54RIkp78OvYxafaw=; b=M13WrF7GiSEdpsQAj8DvzgCZ7vogs68iSdHHseC91e9b/dMlequy1OBFfhGPlKV24T qn72HoS0kR7Xz41ZQxgGtQgPnFeDHj07nWgpHrqpkgIiUjQkAzzafoAmh1Rl0knYq9Io 58jKlOcQ9bbeuVG3MA7WXIWbSNQHd4UsNtFwnLAxJ8UAQiu1XzEPC4NCIzcvqcU+eo0v ltPKbPqNpzXRLu+z80c7w+KH4JgZToKS/kTpqBejdnoqyhYMb8+AjS9jvhnT+ouJfLqV wV1wOh4BZ5+M32lzLQvQ+Pp7m9iC11Poi7uxKxNHIJ7spAhbiYOVKa+rPdPPexGrc6lJ AxVQ== X-Gm-Message-State: AN3rC/7M3JnMI0DolwBlMVYgWbRqjUpVvnJF7LBnTddxP4FzUyAR+Uvp 1DXElJLTEtlqpg== X-Received: by 10.99.151.18 with SMTP id n18mr724925pge.199.1493953311390; Thu, 04 May 2017 20:01:51 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id f6sm6690979pfe.57.2017.05.04.20.01.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 May 2017 20:01:50 -0700 (PDT) From: Kever Yang To: sjg@chromium.org Date: Fri, 5 May 2017 11:01:43 +0800 Message-Id: <1493953303-10128-1-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] rockchip; rk3399: disable SRAM security region X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some host like SD and eMMC may use DMA to transter data to SRAM, set memory to non-secure to make sure the address can be accessed. The security of SRAM in OS suppose to initialized in ATF bl31, and the SPL is before the bl31. Signed-off-by: Kever Yang Acked-by: Simon Glass Acked-by: Simon Glass --- arch/arm/mach-rockchip/rk3399-board-spl.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 050f5e1..e050aff 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -156,8 +156,6 @@ void secure_timer_init(void) writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); } -#define SGRF_DDR_RGN_CON16 0xff330040 - void board_debug_uart_init(void) { #include @@ -188,6 +186,8 @@ void board_debug_uart_init(void) } #define GRF_EMMCCORE_CON11 0xff77f02c +#define SGRF_DDR_RGN_CON16 0xff330040 +#define SGRF_SLV_SECURE_CON4 0xff33e3d0 void board_init_f(ulong dummy) { struct udevice *pinctrl; @@ -207,6 +207,7 @@ void board_init_f(ulong dummy) debug_uart_init(); printascii("U-Boot SPL board init"); #endif + /* Emmc clock generator: disable the clock multipilier */ rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); @@ -217,7 +218,7 @@ void board_init_f(ulong dummy) } /* - * Disable DDR security regions. + * Disable DDR and SRAM security regions. * * As we are entered from the BootROM, the region from * 0x0 through 0xfffff (i.e. the first MB of memory) will @@ -226,6 +227,7 @@ void board_init_f(ulong dummy) * located in this range. */ rk_clrsetreg(SGRF_DDR_RGN_CON16, 0x1FF, 0); + rk_clrreg(SGRF_SLV_SECURE_CON4, 0x2000); secure_timer_init();