From patchwork Wed May 3 23:38:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas MANOCHA X-Patchwork-Id: 758281 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wJFb23RzXz9s0g for ; Thu, 4 May 2017 10:02:38 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 367B2C21C4E; Thu, 4 May 2017 00:01:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4B4F8C21C68; Thu, 4 May 2017 00:01:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0E40EC21C3F; Thu, 4 May 2017 00:00:07 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id A570BC21C3F for ; Thu, 4 May 2017 00:00:04 +0000 (UTC) Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by m0046037.ppops.net (8.16.0.11/8.16.0.11) with SMTP id v43Nxg3B008330; Thu, 4 May 2017 02:00:00 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-.pphosted.com with ESMTP id 2a72nsnxde-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 04 May 2017 02:00:00 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1401831; Thu, 4 May 2017 00:00:00 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag7node3.st.com [10.75.127.21]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id EEA2DE9A; Wed, 3 May 2017 23:59:59 +0000 (GMT) Received: from localhost (10.75.127.51) by SFHDAG7NODE3.st.com (10.75.127.21) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Thu, 4 May 2017 01:59:58 +0200 From: Vikas Manocha To: Date: Wed, 3 May 2017 16:38:55 -0700 Message-ID: <1493854737-4961-3-git-send-email-vikas.manocha@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1493854737-4961-1-git-send-email-vikas.manocha@st.com> References: <1493854737-4961-1-git-send-email-vikas.manocha@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG1NODE2.st.com (10.75.127.2) To SFHDAG7NODE3.st.com (10.75.127.21) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-03_17:, , signatures=0 Cc: Toshifumi NISHINAGA Subject: [U-Boot] [PATCH 2/4] armv7m: add MPU configuration support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Cortex-M archs support option memory protection unit (MPU). MPU is used to set the memory types, attributes, access permissions for different regions, cache policies of the device. e.g. using MPU it is possible to configure memory region as device memory or strongly ordered, memory attributes like execute never, cache policies like write-back or write-through. Signed-off-by: Vikas Manocha --- arch/arm/cpu/armv7m/Makefile | 2 +- arch/arm/cpu/armv7m/mpu.c | 82 +++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/armv7m.h | 20 ---------- arch/arm/include/asm/armv7m_mpu.h | 67 ++++++++++++++++++++++++++++++++ 4 files changed, 150 insertions(+), 21 deletions(-) create mode 100644 arch/arm/cpu/armv7m/mpu.c create mode 100644 arch/arm/include/asm/armv7m_mpu.h diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index 93c9085..257fc7f 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -6,5 +6,5 @@ # extra-y := start.o -obj-y += cpu.o cache.o +obj-y += cpu.o cache.o mpu.o obj-$(CONFIG_SYS_ARCH_TIMER) += systick-timer.o diff --git a/arch/arm/cpu/armv7m/mpu.c b/arch/arm/cpu/armv7m/mpu.c new file mode 100644 index 0000000..31a243b --- /dev/null +++ b/arch/arm/cpu/armv7m/mpu.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define V7M_MPU_CTRL_ENABLE (1 << 0) +#define V7M_MPU_CTRL_DISABLE (0 << 0) +#define V7M_MPU_CTRL_HFNMIENA (1 << 1) +#define VALID_REGION (1 << 4) + +#define ENABLE_REGION (1 << 0) + +#define AP_SHIFT 24 +#define XN_SHIFT 28 +#define TEX_SHIFT 19 +#define S_SHIFT 18 +#define C_SHIFT 17 +#define B_SHIFT 16 +#define REGION_SIZE_SHIFT 1 + +#define CACHEABLE (1 << C_SHIFT) +#define BUFFERABLE (1 << B_SHIFT) +#define SHAREABLE (1 << S_SHIFT) + +void disable_mpu(void) +{ + writel(0, &V7M_MPU->ctrl); +} + +void enable_mpu(void) +{ + writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); + + /* Make sure new mpu config is effective for next memory access */ + dsb(); + isb(); /* Make sure instruction stream sees it */ +} + +void mpu_config(struct mpu_region_config *reg_config) +{ + uint32_t attr; + + switch (reg_config->mr_attr) { + case STRONG_ORDER: + attr = SHAREABLE; + break; + case SHARED_WRITE_BUFFERED: + attr = BUFFERABLE; + break; + case O_I_WT_NO_WR_ALLOC: + attr = CACHEABLE; + break; + case O_I_WB_NO_WR_ALLOC: + attr = CACHEABLE | BUFFERABLE; + break; + case O_I_NON_CACHEABLE: + attr = 1 << TEX_SHIFT; + break; + case O_I_WB_RD_WR_ALLOC: + attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; + break; + case DEVICE_NON_SHARED: + attr = (2 << TEX_SHIFT) | BUFFERABLE; + default: + attr = 0; /* strongly ordered */ + break; + }; + + writel(reg_config->start_addr | VALID_REGION | reg_config->region_no, + &V7M_MPU->rbar); + + writel(reg_config->xn << XN_SHIFT | reg_config->ap << AP_SHIFT | attr + | reg_config->reg_size << REGION_SIZE_SHIFT | ENABLE_REGION + , &V7M_MPU->rasr); +} diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index 9a6224f..af8a97e 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -70,25 +70,5 @@ struct v7m_mpu { }; #define V7M_MPU ((struct v7m_mpu *)V7M_MPU_BASE) -#define V7M_MPU_CTRL_ENABLE (1 << 0) -#define V7M_MPU_CTRL_HFNMIENA (1 << 1) - -#define V7M_MPU_CTRL_ENABLE (1 << 0) -#define V7M_MPU_CTRL_DISABLE (0 << 0) -#define V7M_MPU_CTRL_HFNMIENA (1 << 1) - -#define V7M_MPU_RASR_EN (1 << 0) -#define V7M_MPU_RASR_SIZE_BITS 1 -#define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS) -#define V7M_MPU_RASR_SIZE_8MB (22 << V7M_MPU_RASR_SIZE_BITS) - -#define V7M_MPU_RASR_TEX_SHIFT 19 -#define V7M_MPU_RASR_S_SHIFT 18 -#define V7M_MPU_RASR_C_SHIFT 17 -#define V7M_MPU_RASR_B_SHIFT 16 -#define V7M_MPU_RASR_AP_RW_RW (3 << 24) -#define V7M_MPU_RASR_XN_ENABLE (0 << 28) -#define V7M_MPU_RASR_XN_DISABLE (1 << 28) - #endif /* !defined(__ASSEMBLY__) */ #endif /* ARMV7M_H */ diff --git a/arch/arm/include/asm/armv7m_mpu.h b/arch/arm/include/asm/armv7m_mpu.h new file mode 100644 index 0000000..d7e99b4 --- /dev/null +++ b/arch/arm/include/asm/armv7m_mpu.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +enum region_number { + REGION_0 = 0, + REGION_1, + REGION_2, + REGION_3, + REGION_4, + REGION_5, + REGION_6, + REGION_7, +}; + +enum ap { + NO_ACCESS = 0, + PRIV_RW_USR_NO, + PRIV_RW_USR_RO, + PRIV_RW_USR_RW, + UNPREDICTABLE, + PRIV_RO_USR_NO, + PRIV_RO_USR_RO, +}; + +enum mr_attr { + STRONG_ORDER = 0, + SHARED_WRITE_BUFFERED, + O_I_WT_NO_WR_ALLOC, + O_I_WB_NO_WR_ALLOC, + O_I_NON_CACHEABLE, + O_I_WB_RD_WR_ALLOC, + DEVICE_NON_SHARED, +}; +enum size { + REGION_8MB = 22, + REGION_16MB, + REGION_32MB, + REGION_64MB, + REGION_128MB, + REGION_256MB, + REGION_512MB, + REGION_1GB, + REGION_2GB, + REGION_4GB, +}; + +enum xn { + XN_DIS = 0, + XN_EN, +}; + +struct mpu_region_config { + uint32_t start_addr; + enum region_number region_no; + enum xn xn; + enum ap ap; + enum mr_attr mr_attr; + enum size reg_size; +}; + +void disable_mpu(void); +void enable_mpu(void); +void mpu_config(struct mpu_region_config *reg_config);