From patchwork Mon Apr 24 15:45:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: igall@marvell.com X-Patchwork-Id: 754541 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wBj5w6WBhz9s8Q for ; Tue, 25 Apr 2017 09:21:40 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 9130FC21CDE; Mon, 24 Apr 2017 23:10:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 86C90C21D1A; Mon, 24 Apr 2017 22:59:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4C212C21C27; Mon, 24 Apr 2017 15:47:33 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by lists.denx.de (Postfix) with ESMTPS id AAD3BC21C29 for ; Mon, 24 Apr 2017 15:47:32 +0000 (UTC) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v3OFjHjA018652; Mon, 24 Apr 2017 08:47:29 -0700 Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2a04hkdu1f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 24 Apr 2017 08:47:29 -0700 Received: from IL-EXCH03.marvell.com (10.5.102.220) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 24 Apr 2017 08:47:27 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by IL-EXCH03.marvell.com (10.5.102.220) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 24 Apr 2017 18:47:25 +0300 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 24 Apr 2017 08:47:24 -0700 Received: from igall-OptiPlex-990.pt.marvell.com (unknown [10.5.24.64]) by maili.marvell.com (Postfix) with ESMTP id 609123F7040; Mon, 24 Apr 2017 08:47:23 -0700 (PDT) From: To: Date: Mon, 24 Apr 2017 18:45:25 +0300 Message-ID: <1493048733-22194-6-git-send-email-igall@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493048733-22194-1-git-send-email-igall@marvell.com> References: <1493048733-22194-1-git-send-email-igall@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-24_12:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1704240269 X-Mailman-Approved-At: Mon, 24 Apr 2017 22:58:33 +0000 Cc: Rabeeh Khoury , nadavh@marvell.com, neta@marvell.com, sr@denx.de, Igal Liberman Subject: [U-Boot] [v2, 05/13] fix: phy: marvell: cp110: fix the KR/SFI line 4 selector X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Roese This patch fixes the following: 1. KR/SFI on lane #4 mux selector is 0x2 and not 0x1 2. Comment typo Signed-off-by: Rabeeh Khoury Signed-off-by: Stefan Roese Signed-off-by: Igal Liberman Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_cp110.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 499aa68..e90a913 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -49,7 +49,7 @@ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, + {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x2}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */ {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, @@ -1718,7 +1718,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, } if (ret == 0) { /* - * If interface wans't initialiuzed, set the lane to + * If interface wans't initialized, set the lane to * PHY_TYPE_UNCONNECTED state. */ ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;