From patchwork Mon Apr 24 15:45:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: igall@marvell.com X-Patchwork-Id: 754535 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3wBj2q5lDzz9s8S for ; Tue, 25 Apr 2017 09:18:59 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 5ADDAC21CBF; Mon, 24 Apr 2017 23:09:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 928A1C21D1F; Mon, 24 Apr 2017 22:59:01 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CAEB6C21C2B; Mon, 24 Apr 2017 15:47:29 +0000 (UTC) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lists.denx.de (Postfix) with ESMTPS id 59B61C21C29 for ; Mon, 24 Apr 2017 15:47:29 +0000 (UTC) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v3OFidXm020095; Mon, 24 Apr 2017 08:47:26 -0700 Received: from il-exch02.marvell.com ([199.203.130.102]) by mx0b-0016f401.pphosted.com with ESMTP id 2a06pfvd8w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 24 Apr 2017 08:47:26 -0700 Received: from SC-EXCH02.marvell.com (10.93.176.82) by IL-EXCH02.marvell.com (10.4.102.221) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Mon, 24 Apr 2017 18:47:22 +0300 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Mon, 24 Apr 2017 08:47:22 -0700 Received: from igall-OptiPlex-990.pt.marvell.com (unknown [10.5.24.64]) by maili.marvell.com (Postfix) with ESMTP id 9A24C3F703F; Mon, 24 Apr 2017 08:47:20 -0700 (PDT) From: To: Date: Mon, 24 Apr 2017 18:45:24 +0300 Message-ID: <1493048733-22194-5-git-send-email-igall@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493048733-22194-1-git-send-email-igall@marvell.com> References: <1493048733-22194-1-git-send-email-igall@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-24_12:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1704240269 X-Mailman-Approved-At: Mon, 24 Apr 2017 22:58:33 +0000 Cc: nadavh@marvell.com, neta@marvell.com, sr@denx.de, Igal Liberman Subject: [U-Boot] [v2, 04/13] phy: marvell: add IGNORE COMPHY type X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Roese This type tells u-boot to preserve the COMPHY settings as is it is usefull in situations where the COMPHY was initialized by earlier firmware. Note that IGNORE is different from UNCONNECTED since setting UNCONNECTED type will disconnect the COMPHY in the COMPHY MUX which is a desired behaviour Signed-off-by: Yehuda Yitschak Signed-off-by: Stefan Roese Signed-off-by: Igal Liberman Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_core.c | 2 +- drivers/phy/marvell/comphy_cp110.c | 1 + drivers/phy/marvell/comphy_mux.c | 7 +++++++ include/dt-bindings/comphy/comphy_data.h | 3 ++- 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index db23bef..23e8c4b 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -37,7 +37,7 @@ static char *get_type_string(u32 type) "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", "XAUI0", "XAUI1", "XAUI2", "XAUI3", - "RXAUI0", "RXAUI1", "SFI"}; + "RXAUI0", "RXAUI1", "SFI", "IGNORE"}; if (type < 0 || type > PHY_TYPE_MAX) return "invalid"; diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 8bec0ab..499aa68 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -1663,6 +1663,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, } switch (ptr_comphy_map->type) { case PHY_TYPE_UNCONNECTED: + case PHY_TYPE_IGNORE: continue; break; case PHY_TYPE_PEX0: diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index 1dc7426..b036fb1 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -27,6 +27,10 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { + /* Don't check ignored COMPHYs */ + if (comphy_map_data->type == PHY_TYPE_IGNORE) + continue; + mux_opt = mux_data->mux_values; for (opt = 0, valid = 0; opt < mux_data->max_lane_values; opt++, mux_opt++) { @@ -83,6 +87,9 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { + if (comphy_map_data->type == PHY_TYPE_IGNORE) + continue; + offset = lane * bitcount; mask = (((1 << bitcount) - 1) << offset); value = (comphy_mux_get_mux_value(mux_data, diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index d127388..5eb32ef 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -43,7 +43,8 @@ #define PHY_TYPE_RXAUI0 21 #define PHY_TYPE_RXAUI1 22 #define PHY_TYPE_SFI 23 -#define PHY_TYPE_MAX 24 +#define PHY_TYPE_IGNORE 24 +#define PHY_TYPE_MAX 25 #define PHY_TYPE_INVALID 0xff #define PHY_POLARITY_NO_INVERT 0